AXI4RAM.scala (f320e0f01bd645f0a3045a8a740e60dd770734a9) AXI4RAM.scala (c21bff99db38ffd5df19a9459a048e16b7b7cb23)
1/***************************************************************************************
2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences
3* Copyright (c) 2020-2021 Peng Cheng Laboratory
4*
5* XiangShan is licensed under Mulan PSL v2.
6* You can use this software according to the terms and conditions of the Mulan PSL v2.
7* You may obtain a copy of Mulan PSL v2 at:
8* http://license.coscl.org.cn/MulanPSL2

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14* See the Mulan PSL v2 for more details.
15***************************************************************************************/
16
17package device
18
19import chipsalliance.rocketchip.config.Parameters
20import chisel3._
21import chisel3.util._
1/***************************************************************************************
2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences
3* Copyright (c) 2020-2021 Peng Cheng Laboratory
4*
5* XiangShan is licensed under Mulan PSL v2.
6* You can use this software according to the terms and conditions of the Mulan PSL v2.
7* You may obtain a copy of Mulan PSL v2 at:
8* http://license.coscl.org.cn/MulanPSL2

--- 5 unchanged lines hidden (view full) ---

14* See the Mulan PSL v2 for more details.
15***************************************************************************************/
16
17package device
18
19import chipsalliance.rocketchip.config.Parameters
20import chisel3._
21import chisel3.util._
22import Chisel.BlackBox
22import freechips.rocketchip.amba.axi4.{AXI4SlaveNode, AXI4EdgeParameters, AXI4MasterNode}
23import freechips.rocketchip.diplomacy.{AddressSet, InModuleBody, LazyModule, LazyModuleImp, RegionType}
24import top.HaveAXI4MemPort
25import xiangshan.HasXSParameter
26import utils.MaskExpand
27
28class RAMHelper(memByte: BigInt) extends BlackBox {
29 val DataBits = 64

--- 91 unchanged lines hidden --- 		23import freechips.rocketchip.amba.axi4.{AXI4SlaveNode, AXI4EdgeParameters, AXI4MasterNode}
24import freechips.rocketchip.diplomacy.{AddressSet, InModuleBody, LazyModule, LazyModuleImp, RegionType}
25import top.HaveAXI4MemPort
26import xiangshan.HasXSParameter
27import utils.MaskExpand
28
29class RAMHelper(memByte: BigInt) extends BlackBox {
30 val DataBits = 64

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