Configs.scala (175bcfe9ae63c4f6c46e0386e26656f6fa9fe4d3) Configs.scala (05f23f575dc9b9d5ecb9f7884862bbe593024bf4)
1package top
2
3import chisel3._
4import chisel3.util._
5import xiangshan._
6import utils._
7import system._
8import chipsalliance.rocketchip.config._

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15class DefaultConfig(n: Int) extends Config((site, here, up) => {
16 case XLen => 64
17 case DebugOptionsKey => DebugOptions()
18 case SoCParamsKey => SoCParameters(
19 cores = List.tabulate(n){ i => XSCoreParameters(HartId = i) }
20 )
21})
22
1package top
2
3import chisel3._
4import chisel3.util._
5import xiangshan._
6import utils._
7import system._
8import chipsalliance.rocketchip.config._

--- 6 unchanged lines hidden (view full) ---

15class DefaultConfig(n: Int) extends Config((site, here, up) => {
16 case XLen => 64
17 case DebugOptionsKey => DebugOptions()
18 case SoCParamsKey => SoCParameters(
19 cores = List.tabulate(n){ i => XSCoreParameters(HartId = i) }
20 )
21})
22
23// TODO: disable L2 and L3
23// Synthesizable minimal XiangShan
24// * It is still an out-of-order, super-scalaer arch
25// * L1 cache included
26// * L2 cache NOT included
27// * L3 cache included
24class MinimalConfig(n: Int = 1) extends Config(
25 new DefaultConfig(n).alter((site, here, up) => {
26 case SoCParamsKey => up(SoCParamsKey).copy(
27 cores = up(SoCParamsKey).cores.map(_.copy(
28class MinimalConfig(n: Int = 1) extends Config(
29 new DefaultConfig(n).alter((site, here, up) => {
30 case SoCParamsKey => up(SoCParamsKey).copy(
31 cores = up(SoCParamsKey).cores.map(_.copy(
32 DecodeWidth = 2,
33 RenameWidth = 2,
34 FetchWidth = 4,
28 IssQueSize = 8,
29 NRPhyRegs = 80,
30 LoadQueueSize = 16,
31 StoreQueueSize = 16,
32 RoqSize = 32,
33 BrqSize = 8,
34 FtqSize = 16,
35 IBufSize = 16,
35 IssQueSize = 8,
36 NRPhyRegs = 80,
37 LoadQueueSize = 16,
38 StoreQueueSize = 16,
39 RoqSize = 32,
40 BrqSize = 8,
41 FtqSize = 16,
42 IBufSize = 16,
43 StoreBufferSize = 4,
44 StoreBufferThreshold = 3,
36 dpParams = DispatchParameters(
37 IntDqSize = 8,
38 FpDqSize = 8,
39 LsDqSize = 8,
40 IntDqDeqWidth = 4,
41 FpDqDeqWidth = 4,
42 LsDqDeqWidth = 4
43 ),
45 dpParams = DispatchParameters(
46 IntDqSize = 8,
47 FpDqSize = 8,
48 LsDqSize = 8,
49 IntDqDeqWidth = 4,
50 FpDqDeqWidth = 4,
51 LsDqDeqWidth = 4
52 ),
53 icacheParameters = ICacheParameters(
54 nSets = 8, // 4KB ICache
55 tagECC = Some("parity"),
56 dataECC = Some("parity"),
57 replacer = Some("setplru"),
58 nMissEntries = 2
59 ),
60 dcacheParameters = DCacheParameters(
61 nSets = 8, // 4KB DCache
62 nWays = 4,
63 tagECC = Some("secded"),
64 dataECC = Some("secded"),
65 replacer = Some("setplru"),
66 nMissEntries = 4,
67 nProbeEntries = 4,
68 nReleaseEntries = 4,
69 nStoreReplayEntries = 4,
70 ),
71 L2Size = 16 * 1024, // 16KB
72 L2NWays = 8,
44 EnableBPD = false, // disable TAGE
45 EnableLoop = false,
46 TlbEntrySize = 4,
47 TlbSPEntrySize = 2,
48 PtwL1EntrySize = 2,
73 EnableBPD = false, // disable TAGE
74 EnableLoop = false,
75 TlbEntrySize = 4,
76 TlbSPEntrySize = 2,
77 PtwL1EntrySize = 2,
49 PtwL2EntrySize = 2,
50 PtwL3EntrySize = 4,
78 PtwL2EntrySize = 64,
79 PtwL3EntrySize = 128,
51 PtwSPEntrySize = 2,
80 PtwSPEntrySize = 2,
81 useFakeL2Cache = true,
82 )),
83 L3Size = 32 * 1024, // 32KB
84 )
85 })
86)
87
88// Non-synthesizable MinimalConfig, for fast simulation only
89class MinimalSimConfig(n: Int = 1) extends Config(
90 new MinimalConfig(n).alter((site, here, up) => {
91 case SoCParamsKey => up(SoCParamsKey).copy(
92 cores = up(SoCParamsKey).cores.map(_.copy(
52 useFakeDCache = true,
53 useFakePTW = true,
54 useFakeL1plusCache = true,
55 )),
56 useFakeL3Cache = true
57 )
58 })
59)
93 useFakeDCache = true,
94 useFakePTW = true,
95 useFakeL1plusCache = true,
96 )),
97 useFakeL3Cache = true
98 )
99 })
100)