Configs.scala (8a4dab4daf33dc2dbb0329809bd20ddcc01d0579) Configs.scala (5c06072729ebf9577a23fe84f4eb39de6932028f)
1/***************************************************************************************
2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences
3* Copyright (c) 2020-2021 Peng Cheng Laboratory
4*
5* XiangShan is licensed under Mulan PSL v2.
6* You can use this software according to the terms and conditions of the Mulan PSL v2.
7* You may obtain a copy of Mulan PSL v2 at:
8* http://license.coscl.org.cn/MulanPSL2

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26import freechips.rocketchip.tile.{BusErrorUnit, BusErrorUnitParams, XLen}
27import xiangshan.frontend.icache.ICacheParameters
28import freechips.rocketchip.devices.debug._
29import freechips.rocketchip.tile.{MaxHartIdBits, XLen}
30import system._
31import utility._
32import utils._
33import huancun._
1/***************************************************************************************
2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences
3* Copyright (c) 2020-2021 Peng Cheng Laboratory
4*
5* XiangShan is licensed under Mulan PSL v2.
6* You can use this software according to the terms and conditions of the Mulan PSL v2.
7* You may obtain a copy of Mulan PSL v2 at:
8* http://license.coscl.org.cn/MulanPSL2

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26import freechips.rocketchip.tile.{BusErrorUnit, BusErrorUnitParams, XLen}
27import xiangshan.frontend.icache.ICacheParameters
28import freechips.rocketchip.devices.debug._
29import freechips.rocketchip.tile.{MaxHartIdBits, XLen}
30import system._
31import utility._
32import utils._
33import huancun._
34import openLLC.{OpenLLCParam}
34import xiangshan._
35import xiangshan.backend.dispatch.DispatchParameters
36import xiangshan.backend.regfile.{IntPregParams, VfPregParams}
37import xiangshan.cache.DCacheParameters
38import xiangshan.cache.mmu.{L2TLBParameters, TLBParameters}
39import device.{EnableJtag, XSDebugModuleParams}
40import huancun._
41import coupledL2._

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335 reqField = Seq(utility.ReqSourceField()),
336 sramClkDivBy2 = true,
337 sramDepthDiv = 4,
338 tagECC = Some("secded"),
339 dataECC = Some("secded"),
340 simulation = !site(DebugOptionsKey).FPGAPlatform,
341 prefetch = Some(huancun.prefetch.L3PrefetchReceiverParams()),
342 tpmeta = Some(huancun.prefetch.DefaultTPmetaParameters())
35import xiangshan._
36import xiangshan.backend.dispatch.DispatchParameters
37import xiangshan.backend.regfile.{IntPregParams, VfPregParams}
38import xiangshan.cache.DCacheParameters
39import xiangshan.cache.mmu.{L2TLBParameters, TLBParameters}
40import device.{EnableJtag, XSDebugModuleParams}
41import huancun._
42import coupledL2._

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336 reqField = Seq(utility.ReqSourceField()),
337 sramClkDivBy2 = true,
338 sramDepthDiv = 4,
339 tagECC = Some("secded"),
340 dataECC = Some("secded"),
341 simulation = !site(DebugOptionsKey).FPGAPlatform,
342 prefetch = Some(huancun.prefetch.L3PrefetchReceiverParams()),
343 tpmeta = Some(huancun.prefetch.DefaultTPmetaParameters())
344 )),
345 OpenLLCParamsOpt = Some(OpenLLCParam(
346 name = "LLC",
347 ways = ways,
348 sets = sets,
349 banks = banks,
350 fullAddressBits = 48,
351 clientCaches = tiles.map { core =>
352 val l2params = core.L2CacheParamsOpt.get
353 l2params.copy(sets = 2 * clientDirBytes / core.L2NBanks / l2params.ways / 64, ways = l2params.ways + 2)
354 }
343 ))
344 )
345})
346
347class WithL3DebugConfig extends Config(
348 new WithNKBL3(256, inclusive = false) ++ new WithNKBL2(64)
349)
350

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356 )
357})
358
359class WithL3DebugConfig extends Config(
360 new WithNKBL3(256, inclusive = false) ++ new WithNKBL2(64)
361)
362

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