| Configs.scala (b92f84459b67a53e82d79920469d5fd6d21aad5e) | Configs.scala (78a8cd257caa1ff2b977d80082b1b3a2fa98a1d3) |
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| 1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 --- 277 unchanged lines hidden (view full) --- 286 sets = 2 * p.dcacheParametersOpt.get.nSets / banks, 287 ways = p.dcacheParametersOpt.get.nWays + 2, 288 aliasBitsOpt = p.dcacheParametersOpt.get.aliasBitsOpt, 289 vaddrBitsOpt = Some(p.VAddrBits - log2Up(p.dcacheParametersOpt.get.blockBytes)), 290 isKeywordBitsOpt = p.dcacheParametersOpt.get.isKeywordBitsOpt 291 )), 292 reqField = Seq(utility.ReqSourceField()), 293 echoField = Seq(huancun.DirtyField()), | 1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 --- 277 unchanged lines hidden (view full) --- 286 sets = 2 * p.dcacheParametersOpt.get.nSets / banks, 287 ways = p.dcacheParametersOpt.get.nWays + 2, 288 aliasBitsOpt = p.dcacheParametersOpt.get.aliasBitsOpt, 289 vaddrBitsOpt = Some(p.VAddrBits - log2Up(p.dcacheParametersOpt.get.blockBytes)), 290 isKeywordBitsOpt = p.dcacheParametersOpt.get.isKeywordBitsOpt 291 )), 292 reqField = Seq(utility.ReqSourceField()), 293 echoField = Seq(huancun.DirtyField()), |
| 294 prefetch = Seq(PrefetchReceiverParams(), BOPParameters()) ++ (if (tp) Seq(TPParameters()) else Nil), | 294 prefetch = Seq(BOPParameters()) ++ 295 (if (tp) Seq(TPParameters()) else Nil) ++ 296 (if (p.prefetcher.nonEmpty) Seq(PrefetchReceiverParams()) else Nil), |
| 295 enablePerf = !site(DebugOptionsKey).FPGAPlatform && site(DebugOptionsKey).EnablePerfDebug, 296 enableRollingDB = site(DebugOptionsKey).EnableRollingDB, 297 enableMonitor = site(DebugOptionsKey).AlwaysBasicDB, 298 elaboratedTopDown = !site(DebugOptionsKey).FPGAPlatform 299 )), 300 L2NBanks = banks 301 )) 302}) --- 96 unchanged lines hidden (view full) --- 399 400class KunminghuV2Config(n: Int = 1) extends Config( 401 new WithCHI 402 ++ new Config((site, here, up) => { 403 case SoCParamsKey => up(SoCParamsKey).copy(L3CacheParamsOpt = None) // There will be no L3 404 }) 405 ++ new WithNKBL2(2 * 512, inclusive = true, banks = 4, tp = false) 406 ++ new WithNKBL1D(64, ways = 8) | 297 enablePerf = !site(DebugOptionsKey).FPGAPlatform && site(DebugOptionsKey).EnablePerfDebug, 298 enableRollingDB = site(DebugOptionsKey).EnableRollingDB, 299 enableMonitor = site(DebugOptionsKey).AlwaysBasicDB, 300 elaboratedTopDown = !site(DebugOptionsKey).FPGAPlatform 301 )), 302 L2NBanks = banks 303 )) 304}) --- 96 unchanged lines hidden (view full) --- 401 402class KunminghuV2Config(n: Int = 1) extends Config( 403 new WithCHI 404 ++ new Config((site, here, up) => { 405 case SoCParamsKey => up(SoCParamsKey).copy(L3CacheParamsOpt = None) // There will be no L3 406 }) 407 ++ new WithNKBL2(2 * 512, inclusive = true, banks = 4, tp = false) 408 ++ new WithNKBL1D(64, ways = 8) |
| 407 ++ new BaseConfig(n) | 409 ++ new MinimalConfig(n) |
| 408) | 410) |