Generator.scala (7f37d55fc418d3b4583220e634da7e459802c6d8) Generator.scala (51e45dbbf87325e45ff2af6ca86ed6c7eed04464)
1/***************************************************************************************
2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences
3* Copyright (c) 2020-2021 Peng Cheng Laboratory
4*
5* XiangShan is licensed under Mulan PSL v2.
6* You can use this software according to the terms and conditions of the Mulan PSL v2.
7* You may obtain a copy of Mulan PSL v2 at:
8* http://license.coscl.org.cn/MulanPSL2
9*
10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
13*
14* See the Mulan PSL v2 for more details.
15***************************************************************************************/
16
17package top
18
1/***************************************************************************************
2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences
3* Copyright (c) 2020-2021 Peng Cheng Laboratory
4*
5* XiangShan is licensed under Mulan PSL v2.
6* You can use this software according to the terms and conditions of the Mulan PSL v2.
7* You may obtain a copy of Mulan PSL v2 at:
8* http://license.coscl.org.cn/MulanPSL2
9*
10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
13*
14* See the Mulan PSL v2 for more details.
15***************************************************************************************/
16
17package top
18
19import chisel3.RawModule
20import chisel3.stage.{ChiselCli, ChiselGeneratorAnnotation}
21import firrtl.options.Shell
22import firrtl.stage.{FirrtlCli, RunFirrtlTransformAnnotation}
23import xstransforms._
19import circt.stage._
20import chisel3.stage.ChiselGeneratorAnnotation
21import xiangshan.types._
24
22
25trait XiangShanCli { this: Shell =>
26 parser.note("XiangShan Options")
27 DisablePrintfAnnotation.addOptions(parser)
28 EnablePrintfAnnotation.addOptions(parser)
29 DisableAllPrintAnnotation.addOptions(parser)
30 RemoveAssertAnnotation.addOptions(parser)
31}
32
33class XiangShanStage extends chisel3.stage.ChiselStage {
34 override val shell: Shell = new Shell("xiangshan")
35 with XiangShanCli
36 with ChiselCli
37 with FirrtlCli
38}
39
40abstract class FirrtlCompiler
41case object SFC extends FirrtlCompiler
42case object MFC extends FirrtlCompiler
43
44object Generator {
23object Generator {
24 val chiselVersion = chisel3.BuildInfo.version
45
25
46 def execute(args: Array[String], mod: => RawModule, fc: FirrtlCompiler, firtoolOpts: Array[String]) = {
47 fc match {
48 case MFC =>
49 val sfcXsTransforms = Seq(
50 DisablePrintfAnnotation,
51 EnablePrintfAnnotation,
52 DisableAllPrintAnnotation,
53 RemoveAssertAnnotation
54 )
55 val sfcOptions = sfcXsTransforms.flatMap(_.options.map(_.longOption)) ++
56 sfcXsTransforms.flatMap(_.options.flatMap(_.shortOption))
57 val mfcArgs = args.filter(s => {
58 val option_s = if(s.startsWith("--")){
59 s.replace("--", "")
60 } else if(s.startsWith("-")){
61 s.replace("-", "")
62 } else s
63 val cond = sfcOptions.contains(option_s)
64 if(cond){
65 println(s"[Warnning] SFC Transform Option ${s} will be removed in MFC!")
66 }
67 !cond
68 })
69 (new circt.stage.ChiselStage).execute(mfcArgs, Seq(
70 ChiselGeneratorAnnotation(mod _),
71 circt.stage.CIRCTTargetAnnotation(circt.stage.CIRCTTarget.Verilog)
72 ) ++ firtoolOpts.map(opt => circt.stage.FirtoolOption(opt)))
73 case SFC =>
74 (new XiangShanStage).execute(args, Seq(
75 ChiselGeneratorAnnotation(mod _),
76 RunFirrtlTransformAnnotation(new PrintControl),
77 RunFirrtlTransformAnnotation(new PrintModuleName)
78 ))
79 case _ =>
80 assert(false, s"Unknown firrtl compiler: ${fc.getClass.getName}!")
26 def execute(args: Array[String], mod: => chisel3.RawModule, firtoolOpts: Array[String]) = {
27 val annotations = chiselVersion match {
28 case "3.6.0" => Seq(
29 RunFirrtlTransformAnnotation(new PrintControl),
30 RunFirrtlTransformAnnotation(new PrintModuleName)
31 )
32 case _ => Seq(
33 CIRCTTargetAnnotation(CIRCTTarget.Verilog)
34 ) ++ firtoolOpts.map(opt => FirtoolOption(opt))
81 }
35 }
82 }
83
36
37 (new XiangShanStage).execute(args, ChiselGeneratorAnnotation(mod _) +: annotations)
38 }
84}
39}