DbEntry.scala (8891a219bbc84f568e1d134854d8d5ed86d6d560) | DbEntry.scala (4b0d80d87574e82ba31737496d63ac30bed0d40a) |
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1package xiangshan 2 3import org.chipsalliance.cde.config.Parameters 4import chisel3._ 5import chisel3.util.log2Ceil | 1package xiangshan 2 3import org.chipsalliance.cde.config.Parameters 4import chisel3._ 5import chisel3.util.log2Ceil |
6import xiangshan.backend.rob.{DebugLsInfo, DebugMdpInfo} | 6import xiangshan.backend.ctrlblock.{DebugLsInfo, DebugMdpInfo} |
7import xiangshan.cache.DCacheBundle | 7import xiangshan.cache.DCacheBundle |
8import xiangshan.backend.fu.FuType |
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8 9/** Mem */ 10class LoadMissEntry(implicit p: Parameters) extends DCacheBundle { 11 val timeCnt = UInt(XLEN.W) 12 val robIdx = UInt(log2Ceil(RobSize).W) 13 val paddr = UInt(PAddrBits.W) 14 val vaddr = UInt(VAddrBits.W) 15 // 1:first hit, 2:first miss, 3:second miss --- 35 unchanged lines hidden --- | 9 10/** Mem */ 11class LoadMissEntry(implicit p: Parameters) extends DCacheBundle { 12 val timeCnt = UInt(XLEN.W) 13 val robIdx = UInt(log2Ceil(RobSize).W) 14 val paddr = UInt(PAddrBits.W) 15 val vaddr = UInt(VAddrBits.W) 16 // 1:first hit, 2:first miss, 3:second miss --- 35 unchanged lines hidden --- |