XSTile.scala (0e28018481fa4b29a9d6aa8cedfb51cad5dca421) XSTile.scala (78a8cd257caa1ff2b977d80082b1b3a2fa98a1d3)
1/***************************************************************************************
2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences
3* Copyright (c) 2020-2021 Peng Cheng Laboratory
4*
5* XiangShan is licensed under Mulan PSL v2.
6* You can use this software according to the terms and conditions of the Mulan PSL v2.
7* You may obtain a copy of Mulan PSL v2 at:
8* http://license.coscl.org.cn/MulanPSL2

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33class XSTile()(implicit p: Parameters) extends LazyModule
34 with HasXSParameter
35 with HasSoCParameter
36{
37 override def shouldBeInlined: Boolean = false
38 val core = LazyModule(new XSCore())
39 val l2top = LazyModule(new L2Top())
40
1/***************************************************************************************
2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences
3* Copyright (c) 2020-2021 Peng Cheng Laboratory
4*
5* XiangShan is licensed under Mulan PSL v2.
6* You can use this software according to the terms and conditions of the Mulan PSL v2.
7* You may obtain a copy of Mulan PSL v2 at:
8* http://license.coscl.org.cn/MulanPSL2

--- 24 unchanged lines hidden (view full) ---

33class XSTile()(implicit p: Parameters) extends LazyModule
34 with HasXSParameter
35 with HasSoCParameter
36{
37 override def shouldBeInlined: Boolean = false
38 val core = LazyModule(new XSCore())
39 val l2top = LazyModule(new L2Top())
40
41 val enableCHI = p(EnableCHI)
42 val enableL2 = coreParams.L2CacheParamsOpt.isDefined
43 // =========== Public Ports ============
44 val core_l3_pf_port = core.memBlock.l3_pf_sender_opt
45 val memory_port = if (enableCHI && enableL2) None else Some(l2top.memory_port.get)
46 val tl_uncache = l2top.mmio_port
47 // val axi4_uncache = if (enableCHI) Some(AXI4UserYanker()) else None
48 val beu_int_source = l2top.beu.intNode
49 val core_reset_sink = BundleBridgeSink(Some(() => Reset()))

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99 val robHeadPaddr = Valid(UInt(PAddrBits.W))
100 val l3MissMatch = Input(Bool())
101 }
102 val chi = if (enableCHI) Some(new PortIO) else None
103 val nodeID = if (enableCHI) Some(Input(UInt(NodeIDWidth.W))) else None
104 })
105
106 dontTouch(io.hartId)
41 val enableL2 = coreParams.L2CacheParamsOpt.isDefined
42 // =========== Public Ports ============
43 val core_l3_pf_port = core.memBlock.l3_pf_sender_opt
44 val memory_port = if (enableCHI && enableL2) None else Some(l2top.memory_port.get)
45 val tl_uncache = l2top.mmio_port
46 // val axi4_uncache = if (enableCHI) Some(AXI4UserYanker()) else None
47 val beu_int_source = l2top.beu.intNode
48 val core_reset_sink = BundleBridgeSink(Some(() => Reset()))

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98 val robHeadPaddr = Valid(UInt(PAddrBits.W))
99 val l3MissMatch = Input(Bool())
100 }
101 val chi = if (enableCHI) Some(new PortIO) else None
102 val nodeID = if (enableCHI) Some(Input(UInt(NodeIDWidth.W))) else None
103 })
104
105 dontTouch(io.hartId)
106 if (!io.chi.isEmpty) { dontTouch(io.chi.get) }
107
108 val core_soft_rst = core_reset_sink.in.head._1 // unused
109
110 l2top.module.hartId.fromTile := io.hartId
111 core.module.io.hartId := l2top.module.hartId.toCore
112 core.module.io.reset_vector := l2top.module.reset_vector.toCore
113 l2top.module.reset_vector.fromTile := io.reset_vector
114 l2top.module.cpu_halt.fromCore := core.module.io.cpu_halt

--- 54 unchanged lines hidden --- 		107
108 val core_soft_rst = core_reset_sink.in.head._1 // unused
109
110 l2top.module.hartId.fromTile := io.hartId
111 core.module.io.hartId := l2top.module.hartId.toCore
112 core.module.io.reset_vector := l2top.module.reset_vector.toCore
113 l2top.module.reset_vector.fromTile := io.reset_vector
114 l2top.module.cpu_halt.fromCore := core.module.io.cpu_halt

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