Bundles.scala (864480f4bbbc77728906ce3d162663614c19e20b) Bundles.scala (195ef4a53ab54326d879e884c4e1568f424f2668)
1package xiangshan.backend
2
3import org.chipsalliance.cde.config.Parameters
4import chisel3._
5import chisel3.util.BitPat.bitPatToUInt
6import chisel3.util._
7import utils.BundleUtils.makeValid
8import utils.OptionWrapper

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594
595 def needCancel(og0CancelOH: UInt, og1CancelOH: UInt) : Bool = {
596 if (params.isIQWakeUpSink) {
597 require(
598 og0CancelOH.getWidth == l1ExuOH.get.head.getWidth,
599 s"cancelVecSize: {og0: ${og0CancelOH.getWidth}, og1: ${og1CancelOH.getWidth}}"
600 )
601 val l1Cancel: Bool = l1ExuOH.get.zip(srcTimer.get).map {
1package xiangshan.backend
2
3import org.chipsalliance.cde.config.Parameters
4import chisel3._
5import chisel3.util.BitPat.bitPatToUInt
6import chisel3.util._
7import utils.BundleUtils.makeValid
8import utils.OptionWrapper

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594
595 def needCancel(og0CancelOH: UInt, og1CancelOH: UInt) : Bool = {
596 if (params.isIQWakeUpSink) {
597 require(
598 og0CancelOH.getWidth == l1ExuOH.get.head.getWidth,
599 s"cancelVecSize: {og0: ${og0CancelOH.getWidth}, og1: ${og1CancelOH.getWidth}}"
600 )
601 val l1Cancel: Bool = l1ExuOH.get.zip(srcTimer.get).map {
602 case(exuOH: UInt, srcTimer: UInt) =>
603 (exuOH & og0CancelOH).orR && srcTimer === 1.U
602 case(exuOH: Vec[Bool], srcTimer: UInt) =>
603 (exuOH.asUInt & og0CancelOH).orR && srcTimer === 1.U
604 }.reduce(_ | _)
605 l1Cancel
606 } else {
607 false.B
608 }
609 }
610
611 def fromIssueBundle(source: IssueQueueIssueBundle): Unit = {

--- 282 unchanged lines hidden --- 		604 }.reduce(_ | _)
605 l1Cancel
606 } else {
607 false.B
608 }
609 }
610
611 def fromIssueBundle(source: IssueQueueIssueBundle): Unit = {

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