NewFtq.scala (2448f13750170e02ef82f9187de335a073fca0ae) NewFtq.scala (51981c77c37dd3d7ecd4849a0cfb6b431a922958)
1/***************************************************************************************
2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences
3* Copyright (c) 2020-2021 Peng Cheng Laboratory
4*
5* XiangShan is licensed under Mulan PSL v2.
6* You can use this software according to the terms and conditions of the Mulan PSL v2.
7* You may obtain a copy of Mulan PSL v2 at:
8* http://license.coscl.org.cn/MulanPSL2

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1024 }
1025 }
1026 }
1027
1028 // ****************************************************************
1029 // **************************** to bpu ****************************
1030 // ****************************************************************
1031
1/***************************************************************************************
2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences
3* Copyright (c) 2020-2021 Peng Cheng Laboratory
4*
5* XiangShan is licensed under Mulan PSL v2.
6* You can use this software according to the terms and conditions of the Mulan PSL v2.
7* You may obtain a copy of Mulan PSL v2 at:
8* http://license.coscl.org.cn/MulanPSL2

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1024 }
1025 }
1026 }
1027
1028 // ****************************************************************
1029 // **************************** to bpu ****************************
1030 // ****************************************************************
1031
1032 io.toBpu.redirect <> Mux(fromBackendRedirect.valid, fromBackendRedirect, ifuRedirectToBpu)
1032 io.toBpu.redirect := Mux(fromBackendRedirect.valid, fromBackendRedirect, ifuRedirectToBpu)
1033
1034 val may_have_stall_from_bpu = Wire(Bool())
1035 val bpu_ftb_update_stall = RegInit(0.U(2.W)) // 2-cycle stall, so we need 3 states
1036 may_have_stall_from_bpu := bpu_ftb_update_stall =/= 0.U
1037 val canCommit = !may_have_stall_from_bpu &&
1038 Cat(commitStateQueue(commPtr.value).map(s => {
1039 s === c_invalid || s === c_flushed || s === c_commited
1040 })).andR() &&

--- 469 unchanged lines hidden --- 		1033
1034 val may_have_stall_from_bpu = Wire(Bool())
1035 val bpu_ftb_update_stall = RegInit(0.U(2.W)) // 2-cycle stall, so we need 3 states
1036 may_have_stall_from_bpu := bpu_ftb_update_stall =/= 0.U
1037 val canCommit = !may_have_stall_from_bpu &&
1038 Cat(commitStateQueue(commPtr.value).map(s => {
1039 s === c_invalid || s === c_flushed || s === c_commited
1040 })).andR() &&

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