IntDiv.scala (51981c77c37dd3d7ecd4849a0cfb6b431a922958) IntDiv.scala (51e45dbbf87325e45ff2af6ca86ed6c7eed04464)
1/***************************************************************************************
2 * Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences
3 * Copyright (c) 2020-2021 Peng Cheng Laboratory
4 *
5 * XiangShan is licensed under Mulan PSL v2.
6 * You can use this software according to the terms and conditions of the Mulan PSL v2.
7 * You may obtain a copy of Mulan PSL v2 at:
8 * http://license.coscl.org.cn/MulanPSL2

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18
19import chisel3._
20import chiseltest._
21import chiseltest.ChiselScalatestTester
22import chiseltest.VerilatorBackendAnnotation
23import chiseltest.simulator.VerilatorFlags
24import org.scalatest.flatspec.AnyFlatSpec
25import org.scalatest.matchers.must.Matchers
1/***************************************************************************************
2 * Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences
3 * Copyright (c) 2020-2021 Peng Cheng Laboratory
4 *
5 * XiangShan is licensed under Mulan PSL v2.
6 * You can use this software according to the terms and conditions of the Mulan PSL v2.
7 * You may obtain a copy of Mulan PSL v2 at:
8 * http://license.coscl.org.cn/MulanPSL2

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18
19import chisel3._
20import chiseltest._
21import chiseltest.ChiselScalatestTester
22import chiseltest.VerilatorBackendAnnotation
23import chiseltest.simulator.VerilatorFlags
24import org.scalatest.flatspec.AnyFlatSpec
25import org.scalatest.matchers.must.Matchers
26import firrtl.stage.RunFirrtlTransformAnnotation
27import xstransforms.PrintModuleName
26import xiangshan.test.types._
27import xiangshan.types.PrintModuleName
28
29import xiangshan.backend.fu._
30
31import scala.util.Random
32
33
34class SRT4DividerWrapper extends Module {
35 val io = IO(new Bundle{

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63}
64
65class IntDividerTest extends AnyFlatSpec with ChiselScalatestTester with Matchers {
66 behavior of "srt16 divider"
67 it should "run" in {
68 val rand = new Random(0x14226)
69 val testNum = 1000
70
28
29import xiangshan.backend.fu._
30
31import scala.util.Random
32
33
34class SRT4DividerWrapper extends Module {
35 val io = IO(new Bundle{

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63}
64
65class IntDividerTest extends AnyFlatSpec with ChiselScalatestTester with Matchers {
66 behavior of "srt16 divider"
67 it should "run" in {
68 val rand = new Random(0x14226)
69 val testNum = 1000
70
71 val printModuleNameAnno = chisel3.BuildInfo.version match {
72 case "3.6.0" => Seq(RunFirrtlTransformAnnotation(new PrintModuleName))
73 case _ => Seq()
74 }
75
71 test(new SRT4DividerWrapper).withAnnotations(Seq(VerilatorBackendAnnotation,
72 // LineCoverageAnnotation,
73 // ToggleCoverageAnnotation,
74 VerilatorFlags(Seq(
75 // "--output-split 20", "--output-split-cfuncs 20",
76 "+define+RANDOMIZE_REG_INIT", "+define+RANDOMIZE_MEM_INIT", "--trace")),
76 test(new SRT4DividerWrapper).withAnnotations(Seq(VerilatorBackendAnnotation,
77 // LineCoverageAnnotation,
78 // ToggleCoverageAnnotation,
79 VerilatorFlags(Seq(
80 // "--output-split 20", "--output-split-cfuncs 20",
81 "+define+RANDOMIZE_REG_INIT", "+define+RANDOMIZE_MEM_INIT", "--trace")),
77 RunFirrtlTransformAnnotation(new PrintModuleName))){ m =>
82 ) ++ printModuleNameAnno){ m =>
78 println("Test started!")
79 m.clock.step(20)
80
81 for (i <- 1 to testNum) {
82 m.clock.step(3)
83 m.io.in_ready.expect(true.B)
84 val divisor = rand.nextLong()
85 val dividend = rand.nextLong()

--- 31 unchanged lines hidden --- 		83 println("Test started!")
84 m.clock.step(20)
85
86 for (i <- 1 to testNum) {
87 m.clock.step(3)
88 m.io.in_ready.expect(true.B)
89 val divisor = rand.nextLong()
90 val dividend = rand.nextLong()

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