IntDiv.scala (5931ace35325a644a12f8ea27830a2de7489e7e7) IntDiv.scala (e3da8bad334fc71ba0d72f0607e2e93245ddaece)
1/***************************************************************************************
1/***************************************************************************************
2 * Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences
2 * Copyright (c) 2024 Beijing Institute of Open Source Chip (BOSC)
3 * Copyright (c) 2020-2024 Institute of Computing Technology, Chinese Academy of Sciences
3 * Copyright (c) 2020-2021 Peng Cheng Laboratory
4 *
5 * XiangShan is licensed under Mulan PSL v2.
6 * You can use this software according to the terms and conditions of the Mulan PSL v2.
7 * You may obtain a copy of Mulan PSL v2 at:
8 * http://license.coscl.org.cn/MulanPSL2
9 *
10 * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,

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18
19import chisel3._
20import chiseltest._
21import chiseltest.ChiselScalatestTester
22import chiseltest.VerilatorBackendAnnotation
23import chiseltest.simulator.VerilatorFlags
24import org.scalatest.flatspec.AnyFlatSpec
25import org.scalatest.matchers.must.Matchers
4 * Copyright (c) 2020-2021 Peng Cheng Laboratory
5 *
6 * XiangShan is licensed under Mulan PSL v2.
7 * You can use this software according to the terms and conditions of the Mulan PSL v2.
8 * You may obtain a copy of Mulan PSL v2 at:
9 * http://license.coscl.org.cn/MulanPSL2
10 *
11 * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,

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19
20import chisel3._
21import chiseltest._
22import chiseltest.ChiselScalatestTester
23import chiseltest.VerilatorBackendAnnotation
24import chiseltest.simulator.VerilatorFlags
25import org.scalatest.flatspec.AnyFlatSpec
26import org.scalatest.matchers.must.Matchers
26import xiangshan.test.types._
27import xiangshan.transforms.PrintModuleName
28
29import xiangshan.backend.fu._
30
31import scala.util.Random
32
33
34class SRT4DividerWrapper extends Module {

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63}
64
65class IntDividerTest extends AnyFlatSpec with ChiselScalatestTester with Matchers {
66 behavior of "srt16 divider"
67 it should "run" in {
68 val rand = new Random(0x14226)
69 val testNum = 1000
70
27import xiangshan.transforms.PrintModuleName
28
29import xiangshan.backend.fu._
30
31import scala.util.Random
32
33
34class SRT4DividerWrapper extends Module {

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63}
64
65class IntDividerTest extends AnyFlatSpec with ChiselScalatestTester with Matchers {
66 behavior of "srt16 divider"
67 it should "run" in {
68 val rand = new Random(0x14226)
69 val testNum = 1000
70
71 val printModuleNameAnno = chisel3.BuildInfo.version match {
72 case "3.6.0" => Seq(RunFirrtlTransformAnnotation(new PrintModuleName))
73 case _ => Seq()
74 }
75
76 test(new SRT4DividerWrapper).withAnnotations(Seq(VerilatorBackendAnnotation,
77 // LineCoverageAnnotation,
78 // ToggleCoverageAnnotation,
79 VerilatorFlags(Seq(
80 // "--output-split 20", "--output-split-cfuncs 20",
81 "+define+RANDOMIZE_REG_INIT", "+define+RANDOMIZE_MEM_INIT", "--trace")),
71 test(new SRT4DividerWrapper).withAnnotations(Seq(VerilatorBackendAnnotation,
72 // LineCoverageAnnotation,
73 // ToggleCoverageAnnotation,
74 VerilatorFlags(Seq(
75 // "--output-split 20", "--output-split-cfuncs 20",
76 "+define+RANDOMIZE_REG_INIT", "+define+RANDOMIZE_MEM_INIT", "--trace")),
82 ) ++ printModuleNameAnno){ m =>
77 )){ m =>
83 println("Test started!")
84 m.clock.step(20)
85
86 for (i <- 1 to testNum) {
87 m.clock.step(3)
88 m.io.in_ready.expect(true.B)
89 val divisor = rand.nextLong()
90 val dividend = rand.nextLong()

--- 31 unchanged lines hidden --- 		78 println("Test started!")
79 m.clock.step(20)
80
81 for (i <- 1 to testNum) {
82 m.clock.step(3)
83 m.io.in_ready.expect(true.B)
84 val divisor = rand.nextLong()
85 val dividend = rand.nextLong()

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