IntDiv.scala (9aca92b99bc760501680614d3be4f34b46d9ed2e) IntDiv.scala (51981c77c37dd3d7ecd4849a0cfb6b431a922958)
1/***************************************************************************************
2 * Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences
3 * Copyright (c) 2020-2021 Peng Cheng Laboratory
4 *
5 * XiangShan is licensed under Mulan PSL v2.
6 * You can use this software according to the terms and conditions of the Mulan PSL v2.
7 * You may obtain a copy of Mulan PSL v2 at:
8 * http://license.coscl.org.cn/MulanPSL2

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14 * See the Mulan PSL v2 for more details.
15 ***************************************************************************************/
16
17package futest
18
19import chisel3._
20import chiseltest._
21import chiseltest.ChiselScalatestTester
1/***************************************************************************************
2 * Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences
3 * Copyright (c) 2020-2021 Peng Cheng Laboratory
4 *
5 * XiangShan is licensed under Mulan PSL v2.
6 * You can use this software according to the terms and conditions of the Mulan PSL v2.
7 * You may obtain a copy of Mulan PSL v2 at:
8 * http://license.coscl.org.cn/MulanPSL2

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14 * See the Mulan PSL v2 for more details.
15 ***************************************************************************************/
16
17package futest
18
19import chisel3._
20import chiseltest._
21import chiseltest.ChiselScalatestTester
22import chiseltest.experimental.TestOptionBuilder._
23import chiseltest.internal.{LineCoverageAnnotation, ToggleCoverageAnnotation, VerilatorBackendAnnotation}
24import chiseltest.legacy.backends.verilator.VerilatorFlags
22import chiseltest.VerilatorBackendAnnotation
23import chiseltest.simulator.VerilatorFlags
25import org.scalatest.flatspec.AnyFlatSpec
26import org.scalatest.matchers.must.Matchers
27import firrtl.stage.RunFirrtlTransformAnnotation
28import xstransforms.PrintModuleName
29
30import xiangshan.backend.fu._
31
32import scala.util.Random

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63
64}
65
66class IntDividerTest extends AnyFlatSpec with ChiselScalatestTester with Matchers {
67 behavior of "srt16 divider"
68 it should "run" in {
69 val rand = new Random(0x14226)
70 val testNum = 1000
24import org.scalatest.flatspec.AnyFlatSpec
25import org.scalatest.matchers.must.Matchers
26import firrtl.stage.RunFirrtlTransformAnnotation
27import xstransforms.PrintModuleName
28
29import xiangshan.backend.fu._
30
31import scala.util.Random

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62
63}
64
65class IntDividerTest extends AnyFlatSpec with ChiselScalatestTester with Matchers {
66 behavior of "srt16 divider"
67 it should "run" in {
68 val rand = new Random(0x14226)
69 val testNum = 1000
70
71 test(new SRT4DividerWrapper).withAnnotations(Seq(VerilatorBackendAnnotation,
71 test(new SRT4DividerWrapper).withAnnotations(Seq(VerilatorBackendAnnotation,
72 LineCoverageAnnotation,
73 ToggleCoverageAnnotation,
74 VerilatorFlags(Seq("--output-split 5000", "--output-split-cfuncs 5000",
72 // LineCoverageAnnotation,
73 // ToggleCoverageAnnotation,
74 VerilatorFlags(Seq(
75 // "--output-split 20", "--output-split-cfuncs 20",
75 "+define+RANDOMIZE_REG_INIT", "+define+RANDOMIZE_MEM_INIT", "--trace")),
76 RunFirrtlTransformAnnotation(new PrintModuleName))){ m =>
77 println("Test started!")
78 m.clock.step(20)
79
80 for (i <- 1 to testNum) {
81 m.clock.step(3)
82 m.io.in_ready.expect(true.B)

--- 33 unchanged lines hidden --- 		76 "+define+RANDOMIZE_REG_INIT", "+define+RANDOMIZE_MEM_INIT", "--trace")),
77 RunFirrtlTransformAnnotation(new PrintModuleName))){ m =>
78 println("Test started!")
79 m.clock.step(20)
80
81 for (i <- 1 to testNum) {
82 m.clock.step(3)
83 m.io.in_ready.expect(true.B)

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