dispatch - OpenGrok history log for /XiangShan/src/main/scala/xiangshan/backend/dispatch

Revision	Date	Author	Comments (<<< Hide modified files) (Show modified files >>>)
0a85f766	18-Aug-2020	Yinan Xu <[email protected]>	dispatch2Ls: allow 2Load + 2Store /XiangShan/Makefile /XiangShan/src/main/scala/bus/axi4/AXI4.scala /XiangShan/src/main/scala/bus/axi4/AXI4ToAXI4Lite.scala /XiangShan/src/main/scala/bus/tilelink/Arbiter.scala /XiangShan/src/main/scala/bus/tilelink/FakeTLCache.scala /XiangShan/src/main/scala/bus/tilelink/MMIOTLToAXI4.scala /XiangShan/src/main/scala/bus/tilelink/Metadata.scala /XiangShan/src/main/scala/bus/tilelink/NaiveTL1toN.scala /XiangShan/src/main/scala/bus/tilelink/TLUtilities.scala /XiangShan/src/main/scala/bus/tilelink/TileLink.scala /XiangShan/src/main/scala/system/SoC.scala /XiangShan/src/main/scala/utils/BitUtils.scala /XiangShan/src/main/scala/utils/ECC.scala /XiangShan/src/main/scala/utils/ExcitingUtils.scala /XiangShan/src/main/scala/utils/LogUtils.scala /XiangShan/src/main/scala/utils/LookupTree.scala /XiangShan/src/main/scala/utils/Misc.scala /XiangShan/src/main/scala/utils/Replacement.scala /XiangShan/src/main/scala/xiangshan/XSCore.scala /XiangShan/src/main/scala/xiangshan/backend/decode/Decoder.scala /XiangShan/src/main/scala/xiangshan/backend/decode/isa/RVA.scala Dispatch2Ls.scala /XiangShan/src/main/scala/xiangshan/backend/fu/CSR.scala /XiangShan/src/main/scala/xiangshan/backend/issue/IssueQueue.scala /XiangShan/src/main/scala/xiangshan/cache/AMOALU.scala /XiangShan/src/main/scala/xiangshan/cache/L1Cache.scala /XiangShan/src/main/scala/xiangshan/cache/Mem.scala /XiangShan/src/main/scala/xiangshan/cache/dcache.scala /XiangShan/src/main/scala/xiangshan/cache/dcacheWrapper.scala /XiangShan/src/main/scala/xiangshan/cache/icache.scala /XiangShan/src/main/scala/xiangshan/cache/ldu.scala /XiangShan/src/main/scala/xiangshan/cache/loadMissQueue.scala /XiangShan/src/main/scala/xiangshan/cache/misc.scala /XiangShan/src/main/scala/xiangshan/cache/miscMissQueue.scala /XiangShan/src/main/scala/xiangshan/cache/missQueue.scala /XiangShan/src/main/scala/xiangshan/cache/storeMissQueue.scala /XiangShan/src/main/scala/xiangshan/cache/stu.scala /XiangShan/src/main/scala/xiangshan/cache/uncache.scala /XiangShan/src/main/scala/xiangshan/cache/wbu.scala /XiangShan/src/main/scala/xiangshan/mem/LoadUnit.scala /XiangShan/src/main/scala/xiangshan/mem/Lsroq.scala /XiangShan/src/main/scala/xiangshan/mem/Memend.scala /XiangShan/src/main/scala/xiangshan/mem/MiscUnit.scala /XiangShan/src/main/scala/xiangshan/mem/Sbuffer.scala /XiangShan/src/main/scala/xiangshan/mem/StoreUnit.scala /XiangShan/src/main/scala/xiangshan/package.scala /XiangShan/src/test/scala/top/SimMMIO.scala /XiangShan/src/test/scala/top/XSSim.scala /XiangShan/src/test/scala/xiangshan/backend/exu/DCacheTest.scala
4dd8cbd9	16-Aug-2020	Yinan Xu <[email protected]>	dispatch: remove unnecessary comments /XiangShan/debug/Makefile /XiangShan/debug/cputest.sh /XiangShan/src/main/scala/xiangshan/Bundle.scala /XiangShan/src/main/scala/xiangshan/XSCore.scala /XiangShan/src/main/scala/xiangshan/backend/brq/Brq.scala Dispatch1.scala Dispatch2Fp.scala Dispatch2Int.scala Dispatch2Ls.scala /XiangShan/src/main/scala/xiangshan/frontend/BPU.scala /XiangShan/src/main/scala/xiangshan/frontend/Bim.scala /XiangShan/src/main/scala/xiangshan/frontend/Btb.scala /XiangShan/src/main/scala/xiangshan/frontend/IFU.scala /XiangShan/src/main/scala/xiangshan/frontend/PreDecode.scala /XiangShan/src/main/scala/xiangshan/frontend/RAS.scala /XiangShan/src/main/scala/xiangshan/frontend/Tage.scala /XiangShan/src/main/scala/xiangshan/frontend/uBTB.scala /XiangShan/src/main/scala/xiangshan/mem/LoadUnit.scala /XiangShan/src/main/scala/xiangshan/mem/Lsroq.scala /XiangShan/src/main/scala/xiangshan/mem/Memend.scala /XiangShan/src/test/scala/top/XSSim.scala /XiangShan/src/test/scala/xiangshan/frontend/RASTest.scala
fd7ab71f	15-Aug-2020	Yinan Xu <[email protected]>	dispatch,roq: add perf counter /XiangShan/src/main/scala/xiangshan/Bundle.scala /XiangShan/src/main/scala/xiangshan/backend/decode/DecodeHelper.scala /XiangShan/src/main/scala/xiangshan/backend/decode/Decoder.scala /XiangShan/src/main/scala/xiangshan/backend/decode/isa/RVC.scala Dispatch.scala Dispatch1.scala /XiangShan/src/main/scala/xiangshan/backend/fu/CSR.scala /XiangShan/src/main/scala/xiangshan/backend/roq/Roq.scala /XiangShan/src/main/scala/xiangshan/frontend/BPU.scala /XiangShan/src/main/scala/xiangshan/frontend/Btb.scala /XiangShan/src/main/scala/xiangshan/frontend/FakeICache.scala /XiangShan/src/main/scala/xiangshan/frontend/IFU.scala /XiangShan/src/main/scala/xiangshan/frontend/PreDecode.scala /XiangShan/src/main/scala/xiangshan/frontend/uBTB.scala /XiangShan/src/test/csrc/difftest.cpp
714dba2c	14-Aug-2020	Yinan Xu <[email protected]>	dispatch,roq: add walk and replay perfCnt Dispatch.scala /XiangShan/src/main/scala/xiangshan/backend/fu/CSR.scala /XiangShan/src/main/scala/xiangshan/backend/roq/Roq.scala /XiangShan/src/main/scala/xiangshan/cache/dtlb.scala
0fff0560	14-Aug-2020	Yinan Xu <[email protected]>	dispatch queue: fix dispatchReplayCntReg width /XiangShan/src/main/scala/xiangshan/backend/Backend.scala DispatchQueue.scala
bf7ba3d5	13-Aug-2020	Yinan Xu <[email protected]>	dispatch2: zero extend reverseMapping to ExuCnt index width Dispatch2Fp.scala Dispatch2Int.scala Dispatch2Ls.scala
a5537e40	13-Aug-2020	Yinan Xu <[email protected]>	dispatch queue: set dispatchReplayCnt to size.U when all are replayed DispatchQueue.scala
34bb80ca	13-Aug-2020	Yinan Xu <[email protected]>	dispatch queue: do not update walkCnt if no true replay DispatchQueue.scala
58c80916	13-Aug-2020	Yinan Xu <[email protected]>	dispatch queue: revert, use orR and andR DispatchQueue.scala
bf4f68f6	13-Aug-2020	Yinan Xu <[email protected]>	dispatch queue: fix needReplay and maskedNeedReplay DispatchQueue.scala
0953aabf	12-Aug-2020	Yinan Xu <[email protected]>	dispatch queue: fix extra walk logic DispatchQueue.scala
0b2999cc	12-Aug-2020	Yinan Xu <[email protected]>	dispatch queue: fix extra walk valid logic DispatchQueue.scala
ee93bc08	12-Aug-2020	Yinan Xu <[email protected]>	dispatch queue: walk extra dispatched instructions if dispatch is not in-order /XiangShan/src/main/scala/xiangshan/XSCore.scala DispatchQueue.scala /XiangShan/src/main/scala/xiangshan/backend/issue/IssueQueue.scala /XiangShan/src/main/scala/xiangshan/backend/roq/Roq.scala /XiangShan/src/main/scala/xiangshan/mem/LoadUnit.scala
31528c02	10-Aug-2020	Yinan Xu <[email protected]>	dispatch queue: fix needReplay mask to simplify dispatchReplayCnt DispatchQueue.scala /XiangShan/src/main/scala/xiangshan/cache/dcache.scala /XiangShan/src/main/scala/xiangshan/mem/LoadUnit.scala /XiangShan/src/main/scala/xiangshan/mem/Memend.scala
40e8c11f	09-Aug-2020	Yinan Xu <[email protected]>	dispatch queue: update dispatchPtr invalid condition DispatchQueue.scala /XiangShan/src/test/csrc/ram.cpp
e9c2edfa	09-Aug-2020	Yinan Xu <[email protected]>	dispatch queue: fix dispatchReplayCntReg for nested replay DispatchQueue.scala
1ebbe411	09-Aug-2020	Yinan Xu <[email protected]>	dispatch queue: dont reset dispatchPtr if the entry doesnt need cancel /XiangShan/src/main/scala/xiangshan/backend/brq/Brq.scala DispatchQueue.scala
761164ed	09-Aug-2020	Yinan Xu <[email protected]>	dispatch queue: blocking all queues when one of them is walking /XiangShan/src/main/scala/xiangshan/backend/brq/Brq.scala Dispatch.scala DispatchQueue.scala /XiangShan/src/main/scala/xiangshan/backend/issue/ReservationStation.scala
088eee01	09-Aug-2020	Yinan Xu <[email protected]>	dispatch queue: replay index should start from dispatchPtr - 1.U DispatchQueue.scala
0b52ec3d	09-Aug-2020	Yinan Xu <[email protected]>	dispatch queue: dont reset preg state if idest is 0 DispatchQueue.scala /XiangShan/src/main/scala/xiangshan/backend/rename/BusyTable.scala /XiangShan/src/main/scala/xiangshan/mem/Lsroq.scala
a4f99170	08-Aug-2020	Yinan Xu <[email protected]>	dispatch queue: dont change ptr when no entry is cancelled or replayed DispatchQueue.scala
15ecc572	08-Aug-2020	Yinan Xu <[email protected]>	dispatch queue: fix tailCancelPtr DispatchQueue.scala
f56bb478	08-Aug-2020	Yinan Xu <[email protected]>	dispatch queue: fix replayPregReq logic DispatchQueue.scala
4af96747	08-Aug-2020	Yinan Xu <[email protected]>	dispatch queue: compare cancel distance and replayCnt for nested replay and cancel DispatchQueue.scala
9f5bf9b4	08-Aug-2020	Yinan Xu <[email protected]>	dispatch queue: fix dispatchPtr,dispatchReplayCntReg update when nested replay and cancel DispatchQueue.scala
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