dispatch - OpenGrok history log for /XiangShan/src/main/scala/xiangshan/backend/dispatch

Revision	Date	Author	Comments (<<< Hide modified files) (Show modified files >>>)
b0b6b9bf	01-Aug-2020	Yinan Xu <[email protected]>	dispatch1: fix orderedEnqueue condition Dispatch1.scala /XiangShan/src/main/scala/xiangshan/backend/issue/IssueQueue.scala /XiangShan/src/main/scala/xiangshan/backend/rename/Rename.scala /XiangShan/src/main/scala/xiangshan/mem/cache/dtlb.scala
559a34ff	31-Jul-2020	Yinan Xu <[email protected]>	dispatch1: fix enqFire condition Dispatch1.scala /XiangShan/src/main/scala/xiangshan/backend/issue/IssueQueue.scala
2a4985eb	31-Jul-2020	Yinan Xu <[email protected]>	lsu: fix flush /XiangShan/src/main/scala/xiangshan/Bundle.scala /XiangShan/src/main/scala/xiangshan/backend/Backend.scala Dispatch1.scala /XiangShan/src/main/scala/xiangshan/backend/issue/IssueQueue.scala /XiangShan/src/main/scala/xiangshan/mem/MemPipeline.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/Lsroq.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/Lsu.scala /XiangShan/src/test/scala/xiangshan/backend/issue/IssueQueueTest.scala
7fb75b4f	31-Jul-2020	Yinan Xu <[email protected]>	dispatch1: send roq index to lsroq, fix reg mux Dispatch1.scala
7f8272c4	31-Jul-2020	Yinan Xu <[email protected]>	dispatch2: add dispatch2fp /XiangShan/src/main/scala/xiangshan/backend/Backend.scala Dispatch.scala Dispatch2Fp.scala Dispatch2Int.scala Dispatch2Ls.scala /XiangShan/src/main/scala/xiangshan/mem/cache/dcache.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/Lsroq.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/Lsu.scala
ee2bcd08	30-Jul-2020	William Wang <[email protected]>	Dispatch: send roqIdx from roq to lsroq Dispatch1.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/Lsroq.scala
c047c614	30-Jul-2020	Yinan Xu <[email protected]>	dispatch2ls: disable unuseful comment Dispatch2Ls.scala
cf94fbe8	30-Jul-2020	Yinan Xu <[email protected]>	dispatch2: fix reverse index generation logic Dispatch2Int.scala Dispatch2Ls.scala DispatchQueue.scala IndexMapping.scala /XiangShan/src/main/scala/xiangshan/backend/roq/Roq.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/Lsroq.scala
159180d1	30-Jul-2020	Yinan Xu <[email protected]>	dispatch2ls: disable load1 and store1 Dispatch2Ls.scala
8add929a	30-Jul-2020	Yinan Xu <[email protected]>	dispatch queue: dont move dispatch when walk DispatchQueue.scala
e47c5f02	30-Jul-2020	Yinan Xu <[email protected]>	dispatch: init state with s_invalid and fix cancelled bug /XiangShan/src/main/scala/xiangshan/Bundle.scala /XiangShan/src/main/scala/xiangshan/backend/Backend.scala Dispatch1.scala Dispatch2Int.scala DispatchQueue.scala /XiangShan/src/main/scala/xiangshan/backend/exu/Exu.scala /XiangShan/src/main/scala/xiangshan/backend/exu/Wbu.scala /XiangShan/src/main/scala/xiangshan/backend/issue/IssueQueue.scala /XiangShan/src/main/scala/xiangshan/backend/issue/ReservationStation.scala /XiangShan/src/test/scala/xiangshan/backend/issue/IssueQueueTest.scala /XiangShan/src/test/scala/xiangshan/backend/issue/ReservationStationTest.scala
24a720a9	30-Jul-2020	Yinan Xu <[email protected]>	dispatch queue: fix >= logic DispatchQueue.scala /XiangShan/src/main/scala/xiangshan/mem/MemPipeline.scala /XiangShan/src/main/scala/xiangshan/mem/cache/dcache.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/Lsroq.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/Lsu.scala /XiangShan/src/test/csrc/emu.h
dcc44938	29-Jul-2020	Yinan Xu <[email protected]>	dispatch1: in-order enqueue Dispatch1.scala DispatchQueue.scala
518d8658	29-Jul-2020	Yinan Xu <[email protected]>	dispatch queue: support replay and commit /XiangShan/src/main/scala/xiangshan/Bundle.scala /XiangShan/src/main/scala/xiangshan/XSCore.scala /XiangShan/src/main/scala/xiangshan/backend/Backend.scala Dispatch.scala Dispatch1.scala DispatchQueue.scala /XiangShan/src/main/scala/xiangshan/package.scala
24888f21	29-Jul-2020	Yinan Xu <[email protected]>	dispatch2ls: fix indexVec Dispatch2Ls.scala
bb411583	29-Jul-2020	Yinan Xu <[email protected]>	Merge remote-tracking branch 'origin/temp-lsu-test' into dev-new-dispatch /XiangShan/src/main/scala/xiangshan/Bundle.scala /XiangShan/src/main/scala/xiangshan/XSCore.scala /XiangShan/src/main/scala/xiangshan/backend/Backend.scala /XiangShan/src/main/scala/xiangshan/backend/brq/Brq.scala /XiangShan/src/main/scala/xiangshan/backend/decode/DecodeStage.scala /XiangShan/src/main/scala/xiangshan/backend/decode/Decoder.scala Dispatch.scala DispatchQueue.scala /XiangShan/src/main/scala/xiangshan/backend/exu/AluExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/exu/Exu.scala /XiangShan/src/main/scala/xiangshan/backend/exu/JmpExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Alu.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Divider.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Jump.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Multiplier.scala /XiangShan/src/main/scala/xiangshan/backend/issue/ReservationStation.scala /XiangShan/src/main/scala/xiangshan/backend/rename/FreeList.scala /XiangShan/src/main/scala/xiangshan/backend/roq/Roq.scala /XiangShan/src/main/scala/xiangshan/frontend/BPU.scala /XiangShan/src/main/scala/xiangshan/frontend/Frontend.scala /XiangShan/src/main/scala/xiangshan/frontend/IFU.scala /XiangShan/src/main/scala/xiangshan/frontend/Ibuffer.scala /XiangShan/src/main/scala/xiangshan/frontend/Tage.scala /XiangShan/src/main/scala/xiangshan/frontend/btb.scala /XiangShan/src/main/scala/xiangshan/frontend/jbtac.scala /XiangShan/src/main/scala/xiangshan/mem/MemPipeline.scala /XiangShan/src/main/scala/xiangshan/mem/cache/dcache.scala /XiangShan/src/main/scala/xiangshan/mem/cache/refill.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/Lsroq.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/Lsu.scala /XiangShan/src/test/scala/xiangshan/backend/brq/BrqTest.scala /XiangShan/src/test/scala/xiangshan/frontend/IFUTest.scala
452bca21	29-Jul-2020	Yinan Xu <[email protected]>	dispatch2ls: fix srcState from fp Dispatch.scala Dispatch2Ls.scala
b4278980	29-Jul-2020	Yinan Xu <[email protected]>	dispatch2: replace dispatch2 with int/fp/ls dispatch2 Dispatch.scala Dispatch2Ls.scala
5a84dde5	29-Jul-2020	LinJiawei <[email protected]>	mem: add replay /XiangShan/src/main/scala/xiangshan/Bundle.scala /XiangShan/src/main/scala/xiangshan/backend/Backend.scala /XiangShan/src/main/scala/xiangshan/backend/brq/Brq.scala Dispatch.scala DispatchQueue.scala /XiangShan/src/main/scala/xiangshan/backend/exu/AluExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Divider.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Jump.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Multiplier.scala /XiangShan/src/main/scala/xiangshan/backend/issue/ReservationStation.scala /XiangShan/src/main/scala/xiangshan/mem/MemPipeline.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/Lsroq.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/Lsu.scala
f01f8323	29-Jul-2020	Yinan Xu <[email protected]>	dispatch2: add ls logic Dispatch2Int.scala Dispatch2Ls.scala
6e962ad0	29-Jul-2020	LinJiawei <[email protected]>	Merge refactor-redirect into temp-lsu-test /XiangShan/src/main/scala/xiangshan/Bundle.scala /XiangShan/src/main/scala/xiangshan/XSCore.scala /XiangShan/src/main/scala/xiangshan/backend/Backend.scala /XiangShan/src/main/scala/xiangshan/backend/brq/Brq.scala /XiangShan/src/main/scala/xiangshan/backend/decode/DecodeStage.scala /XiangShan/src/main/scala/xiangshan/backend/decode/Decoder.scala DispatchQueue.scala /XiangShan/src/main/scala/xiangshan/backend/exu/AluExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/exu/Exu.scala /XiangShan/src/main/scala/xiangshan/backend/exu/JmpExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Alu.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Divider.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Jump.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Multiplier.scala /XiangShan/src/main/scala/xiangshan/backend/issue/ReservationStation.scala /XiangShan/src/main/scala/xiangshan/backend/rename/FreeList.scala /XiangShan/src/main/scala/xiangshan/backend/roq/Roq.scala /XiangShan/src/main/scala/xiangshan/frontend/BPU.scala /XiangShan/src/main/scala/xiangshan/frontend/Frontend.scala /XiangShan/src/main/scala/xiangshan/frontend/IFU.scala /XiangShan/src/main/scala/xiangshan/frontend/Ibuffer.scala /XiangShan/src/main/scala/xiangshan/frontend/Tage.scala /XiangShan/src/main/scala/xiangshan/frontend/btb.scala /XiangShan/src/main/scala/xiangshan/frontend/jbtac.scala /XiangShan/src/main/scala/xiangshan/mem/MemPipeline.scala /XiangShan/src/main/scala/xiangshan/mem/cache/dcache.scala /XiangShan/src/main/scala/xiangshan/mem/cache/refill.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/Lsroq.scala /XiangShan/src/main/scala/xiangshan/mem/pipeline/Lsu.scala /XiangShan/src/test/scala/xiangshan/backend/brq/BrqTest.scala /XiangShan/src/test/scala/xiangshan/frontend/IFUTest.scala
250b716d	29-Jul-2020	Yinan Xu <[email protected]>	dispatch2: refactor logic /XiangShan/src/main/scala/xiangshan/XSCore.scala /XiangShan/src/main/scala/xiangshan/backend/Backend.scala Dispatch.scala Dispatch1.scala Dispatch2.scala Dispatch2Int.scala DispatchQueue.scala IndexMapping.scala /XiangShan/src/main/scala/xiangshan/backend/issue/ReservationStation.scala
662adf3b	29-Jul-2020	LinJiawei <[email protected]>	Dispatch: fix flush bug /XiangShan/src/main/scala/xiangshan/backend/brq/Brq.scala Dispatch1.scala /XiangShan/src/main/scala/xiangshan/backend/rename/FreeList.scala
b2e6921e	28-Jul-2020	LinJiawei <[email protected]>	Refactor redirect, cputest pass, microbench fail /XiangShan/.github/workflows/emu.yml /XiangShan/Makefile /XiangShan/debug/Makefile /XiangShan/scripts/statistics.py /XiangShan/src/main/scala/system/SoC.scala /XiangShan/src/main/scala/xiangshan/Bundle.scala /XiangShan/src/main/scala/xiangshan/XSCore.scala /XiangShan/src/main/scala/xiangshan/backend/Backend.scala /XiangShan/src/main/scala/xiangshan/backend/brq/Brq.scala /XiangShan/src/main/scala/xiangshan/backend/decode/DecodeStage.scala /XiangShan/src/main/scala/xiangshan/backend/decode/Decoder.scala Dispatch1.scala DispatchQueue.scala /XiangShan/src/main/scala/xiangshan/backend/exu/AluExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/exu/Exu.scala /XiangShan/src/main/scala/xiangshan/backend/exu/JmpExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/exu/LsExeUnit.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Alu.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Divider.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Jump.scala /XiangShan/src/main/scala/xiangshan/backend/fu/Multiplier.scala /XiangShan/src/main/scala/xiangshan/backend/issue/IssueQueue.scala /XiangShan/src/main/scala/xiangshan/backend/roq/Roq.scala /XiangShan/src/main/scala/xiangshan/frontend/BPU.scala /XiangShan/src/main/scala/xiangshan/frontend/FakeICache.scala /XiangShan/src/main/scala/xiangshan/frontend/Frontend.scala /XiangShan/src/main/scala/xiangshan/frontend/IFU.scala /XiangShan/src/main/scala/xiangshan/frontend/Ibuffer.scala /XiangShan/src/main/scala/xiangshan/frontend/Tage.scala /XiangShan/src/main/scala/xiangshan/frontend/btb.scala /XiangShan/src/main/scala/xiangshan/frontend/jbtac.scala /XiangShan/src/test/csrc/difftest.cpp /XiangShan/src/test/csrc/difftest.h /XiangShan/src/test/csrc/emu.h /XiangShan/src/test/csrc/main.cpp /XiangShan/src/test/csrc/monitor.cpp /XiangShan/src/test/csrc/ram.cpp /XiangShan/src/test/csrc/snapshot.cpp /XiangShan/src/test/csrc/vga.cpp /XiangShan/src/test/scala/xiangshan/backend/brq/BrqTest.scala /XiangShan/src/test/scala/xiangshan/backend/exu/LsuTest.scala /XiangShan/src/test/scala/xiangshan/backend/exu/MduTest.scala /XiangShan/src/test/scala/xiangshan/backend/issue/IssueQueueTest.scala /XiangShan/src/test/scala/xiangshan/frontend/IFUTest.scala /XiangShan/src/test/scala/xiangshan/testutils/AddSinks.scala /XiangShan/src/test/testcase/Makefile /XiangShan/src/test/testcase/tests/double-loop.c /XiangShan/src/test/testcase/tests/nested-loop.c
6c276f18	28-Jul-2020	Yinan Xu <[email protected]>	dispatch: refactor interface Dispatch1.scala Dispatch2.scala DispatchGen.scala RegfileReadPortGen.scala
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