Lines Matching +full:- +full:vv
8 * http://www.apache.org/licenses/LICENSE-2.0
19 #include "android-base/logging.h"
20 #include "android-base/stringprintf.h"
97 return static_cast<int32_t>(imm12) - static_cast<int32_t>(sign << 12); // Sign-extend. in Decode32Imm12()
109 return static_cast<int32_t>(imm) - static_cast<int32_t>(bit11 << 12); // Sign-extend. in Decode32StoreOffset()
129 // Re-orders raw immediatate into real value
136 // Re-orders raw immediatate to form real value
143 // Re-orders raw immediatate to form real value
150 // Re-orders raw immediatate to form real value
161 return static_cast<int32_t>(bits) - static_cast<int32_t>(sign_bit << kWidth); in SignExtendBits()
166 // and performs sign-extension if required
236 "tr", // s1/tr - ART thread register in XRegName()
348 ".rne", ".rtz", ".rdn", ".rup", ".rmm", ".<reserved-rm>", ".<reserved-rm>", /*DYN*/ "" in RoundingModeName()
368 disassembler_->GetDisassemblerOptions()->thread_offset_name_function_( in PrintLoadStoreAddress()
375 // TODO(riscv64): Should we also print the actual sign-extend value? in Print32Lui()
399 int32_t offset = static_cast<int32_t>(imm) - static_cast<int32_t>(bit20 << 21); // Sign-extend. in Print32Jal()
401 os_ << " ; " << disassembler_->FormatInstructionPointer(insn + offset); in Print32Jal()
403 // TODO(riscv64): When we implement shared thunks to reduce AOT slow-path code size, in Print32Jal()
425 // Use the same format as llvm-objdump: "rs1" if `imm12` is zero, otherwise "imm12(rs1)". in Print32Jalr()
465 int32_t offset = static_cast<int32_t>(imm) - static_cast<int32_t>(bit12 << 13); // Sign-extend. in Print32BCond()
467 os_ << " ; " << disassembler_->FormatInstructionPointer(insn + offset); in Print32BCond()
527 case 0b00000: // Vector Unit-Stride Load/Store in DecodeRVVMemMnemonic()
562 case 0b01011: // Vector Unit-Stride Mask Load/Store in DecodeRVVMemMnemonic()
568 case 0b10000: // Vector Unit-Stride Fault-Only-First Load in DecodeRVVMemMnemonic()
721 os_ << "nop"; // Only canonical nop. Non-Zero `rd == rs1` nops are printed as "mv". in Print32BinOpImm()
725 } else if (!narrow && funct3 == /*XORI*/ 4u && imm == -1) { in Print32BinOpImm()
823 DCHECK(kZbbNegOpcodes[funct3 - 4u] != nullptr); in Print32BinOp()
824 os_ << kZbbNegOpcodes[funct3 - 4u]; in Print32BinOp()
827 DCHECK(kZbbMinMaxOpcodes[funct3 - 4u] != nullptr); in Print32BinOp()
828 os_ << kZbbMinMaxOpcodes[funct3 - 4u]; in Print32BinOp()
853 if ((funct3 != 2u && funct3 != 3u) || // There are only 32-bit and 64-bit LR/SC/AMO*. in Print32Atomic()
854 (((funct5 & 3u) != 0u) && funct5 >= 4u)) { // Only multiples of 4, or 1-3. in Print32Atomic()
1037 // TODO(riscv64): Print pseudo-instruction aliases when applicable. in Print32RVVOp()
1052 "vadd.vv", nullptr, "vsub.vv", nullptr, in Print32RVVOp()
1053 "vminu.vv", "vmin.vv", "vmaxu.vv", "vmax.vv", in Print32RVVOp()
1054 nullptr, "vand.vv", "vor.vv", "vxor.vv", in Print32RVVOp()
1055 "vrgather.vv", nullptr, "vrgatherei16.vv", nullptr, in Print32RVVOp()
1058 "vmseq.vv", "vmsne.vv", "vmsltu.vv", "vmslt.vv", in Print32RVVOp()
1059 "vmsleu.vv", "vmsle.vv", nullptr, nullptr, in Print32RVVOp()
1060 "vsaddu.vv", "vsadd.vv", "vssubu.vv", "vssub.vv", in Print32RVVOp()
1061 nullptr, "vsll.vv", nullptr, "vsmul.vv", in Print32RVVOp()
1062 "vsrl.vv", "vsra.vv", "vssrl.vv", "vssra.vv", in Print32RVVOp()
1233 "vaaddu.vv", "vaadd.vv", "vasubu.vv", "vasub.vv", in Print32RVVOp()
1239 "vdivu.vv", "vdiv.vv", "vremu.vv", "vrem.vv", in Print32RVVOp()
1240 "vmulhu.vv", "vmul.vv", "vmulhsu.vv", "vmulh.vv", in Print32RVVOp()
1241 nullptr, "vmadd.vv", nullptr, "vnmsub.vv", in Print32RVVOp()
1242 nullptr, "vmacc.vv", nullptr, "vnmsac.vv", in Print32RVVOp()
1243 "vwaddu.vv", "vwadd.vv", "vwsubu.vv", "vwsub.vv", in Print32RVVOp()
1245 "vwmulu.vv", nullptr, "vwmulsu.vv", "vwmul.vv", in Print32RVVOp()
1246 "vwmaccu.vv", "vwmacc.vv", nullptr, "vwmaccsu.vv", in Print32RVVOp()
1349 "vfadd.vv", "vfredusum.vs", "vfsub.vv", "vfredosum.vs", in Print32RVVOp()
1350 "vfmin.vv", "vfredmin.vs", "vfmax.vv", "vfredmax.vs", in Print32RVVOp()
1351 "vfsgnj.vv", "vfsgnjn.vv", "vfsgnjx.vv", nullptr, in Print32RVVOp()
1355 "vmfeq.vv", "vmfle.vv", nullptr, "vmflt.vv", in Print32RVVOp()
1356 "vmfne.vv", nullptr, nullptr, nullptr, in Print32RVVOp()
1357 "vfdiv.vv", nullptr, nullptr, nullptr, in Print32RVVOp()
1358 "vfmul.vv", nullptr, nullptr, nullptr, in Print32RVVOp()
1359 "vfmadd.vv", "vfnmadd.vv", "vfmsub.vv", "vfnmsub.vv", in Print32RVVOp()
1360 "vfmacc.vv", "vfnmacc.vv", "vfmsac.vv", "vfnmsac.vv", in Print32RVVOp()
1361 "vfwadd.vv", "vfwredusum.vs", "vfwsub.vv", "vfwredosum.vs", in Print32RVVOp()
1363 "vfwmul.vv", nullptr, nullptr, nullptr, in Print32RVVOp()
1364 "vfwmacc.vv", "vfwnmacc.vv", "vfwmsac.vv", "vfwnmsac.vv", in Print32RVVOp()
1573 os_ << disassembler_->FormatInstructionPointer(insn) << StringPrintf(": %08x\t", insn32); in Dump32()
1654 os_ << disassembler_->FormatInstructionPointer(insn) << StringPrintf(": %04x \t", insn16); in Dump16()
1657 int32_t offset = -1; in Dump16()
1787 // sign-extend bits and mask with 0xfffff as llvm-objdump does in Dump16()
1974 os_ << disassembler_->FormatInstructionPointer(data) in Dump2Byte()
1980 os_ << disassembler_->FormatInstructionPointer(data) in DumpByte()
1985 if (begin < GetDisassemblerOptions()->base_address_ || in Dump()
1986 begin >= GetDisassemblerOptions()->end_address_) { in Dump()
1990 if (!IsAligned<2u>(begin) || GetDisassemblerOptions()->end_address_ - begin == 1) { in Dump()
1995 if (GetDisassemblerOptions()->end_address_ - begin >= 4) { in Dump()
2019 while (end - cur >= 4) { in Dump()
2028 if (end - cur >= 2) { in Dump()
2030 // Not enough data for a 32-bit instruction. Dump as `.2byte`. in Dump()
2038 CHECK_EQ(end - cur, 1); in Dump()