Lines Matching full:cpu
1 Arm CPU Specific Build Macros
4 This document describes the various build options present in the CPU specific
6 for a specific CPU on a platform.
29 platform contains at least 1 CPU that requires dynamic mitigation.
34 least 1 CPU that requires this mitigation. Defaults to 1.
38 CPU Errata Workarounds
42 are applied to each CPU by the reset handler. The errata details can be found
43 in the CPU specific errata documents published by Arm:
54 is for example ``A57`` for the ``Cortex_A57`` CPU.
62 these workarounds are enabled for the wrong CPU revision then the errata
76 CPU. This needs to be enabled for all revisions of the CPU.
81 CPU. This needs to be enabled only for revision >= r3p0 of the CPU.
84 CPU. This needs to be enabled only for revision >= r3p0 of the CPU.
89 CPU. This needs to be enabled only for revision <= r1p2 of the CPU.
92 CPU. This needs to be enabled only for revision <= r1p2 of the CPU.
108 CPU. This needs to be enabled only for revision <= r0p2 of the CPU.
114 link time to Cortex-A53 CPU. This needs to be enabled for some variants of
119 CPU. This needs to be enabled only for revision <= r0p3 of the CPU. From
124 to Cortex-A53 CPU. This needs to be enabled for some variants of revision
129 CPUs. Though the erratum is present in every revision of the CPU,
132 Earlier revisions of the CPU have other errata which require the same
136 revisions of Cortex-A53 CPU.
141 CPU. This needs to be enabled only for revision r0p0 of the CPU.
144 CPU. This needs to be enabled only for revision r0p0 of the CPU.
147 CPU. This needs to be enabled only for revision r0p0 of the CPU.
150 CPU. This needs to be enabled only for revision <= r0p1 of the CPU.
153 CPU. This needs to be enabled only for revision <= r0p1 of the CPU.
156 CPU. This needs to be enabled only for revision <= r1p0 of the CPU.
159 revisions of Cortex-A55 CPU.
164 CPU. This needs to be enabled only for revision r0p0 of the CPU.
167 CPU. This needs to be enabled only for revision r0p0 of the CPU.
170 CPU. This needs to be enabled only for revision r0p0 of the CPU.
173 CPU. This needs to be enabled only for revision r0p0 of the CPU.
176 CPU. This needs to be enabled only for revision <= r0p1 of the CPU.
179 CPU. This needs to be enabled only for revision <= r1p1 of the CPU.
182 CPU. This needs to be enabled only for revision <= r1p1 of the CPU.
185 CPU. This needs to be enabled only for revision <= r1p1 of the CPU.
188 CPU. This needs to be enabled only for revision <= r1p2 of the CPU.
191 CPU. This needs to be enabled only for revision <= r1p2 of the CPU.
194 CPU. This needs to be enabled only for revision <= r1p3 of the CPU.
197 revisions of Cortex-A57 CPU.
202 CPU. This needs to be enabled only for revision <= r0p3 of the CPU.
205 revisions of Cortex-A72 CPU.
210 CPU. This needs to be enabled only for revision r0p0 of the CPU.
213 CPU. This needs to be enabled only for revision <= r0p1 of the CPU.
218 CPU. This needs to be enabled only for revision r0p0 of the CPU.
221 CPU. This needs to be enabled only for revision r0p0 of the CPU.
226 CPU. This needs to be enabled only for revision <= r1p0 of the CPU.
229 CPU. This needs to be enabled only for revision <= r2p0 of the CPU.
232 CPU. This needs to be enabled only for revision <= r2p0 of the CPU.
235 CPU. This needs to be enabled only for revision <= r3p0 of the CPU.
238 CPU. This needs to be enabled only for revision <= r3p0 of the CPU.
241 CPU. This needs to be enabled only for revision <= r3p0 of the CPU.
244 CPU. This needs to be enabled only for revision <= r3p0 of the CPU.
247 CPU. This needs to be enabled only for revision <= r4p0 of the CPU.
250 revisions of Cortex-A76 CPU. This errata is fixed in r3p0 but due to
252 of Cortex-A76 CPU.
255 CPU. This needs to be enabled only for revision <= r4p0 of the CPU.
258 CPU. This needs to be enabled only for revisions r3p0 - r4p1 of the CPU.
261 CPU. This needs to be enabled for all revisions <= r4p1 of the CPU and is
267 CPU. This needs to be enabled only for revision <= r1p0 of the CPU.
270 CPU. This needs to be enabled only for revision <= r1p1 of the CPU.
273 CPU. This needs to be enabled only for revision <= r1p1 of the CPU.
276 CPU. This needs to be enabled for r0p0, r1p0, and r1p1, it is still open.
279 CPU. This needs to be enabled for r0p0, r1p0, and r1p1, it is still open.
282 CPU. This needs to be enabled for revisions <= r1p1 of the CPU.
285 CPU. This needs to be enabled for r0p0, r1p0, and r1p1, it is still open.
290 CPU. This needs to be enabled only for revision r0p0 - r1p0 of the CPU.
293 CPU. This needs to be enabled for revisions r0p0, r1p0, and r1p1 of the CPU.
296 CPU. This needs to be enabled for revisions r1p0 and r1p1, r0p0 has the same
300 CPU. This needs to be enabled for revisions r0p0 and r1p0.
303 CPU. This needs to be enabled for revision r0p0, it is fixed in r1p0.
306 CPU. This needs to be enabled for revisions r0p0, r1p0, r1p1, and r1p2. It
310 CPU. This needs to be enabled for revisions r1p0, r1p1, and r1p2. The issue
314 CPU. This needs to be enabled for revisions r0p0, r1p0, r1p1, and r1p2, and
318 CPU. This needs to be enabled for revisions r0p0, r1p0, r1p1, and r1p2, and
322 CPU, this erratum affects system configurations that do not use an ARM
327 CPU. This needs to be enabled for revisions r0p0, r1p0, r1p1 and r1p2 and
331 CPU. This needs to be enabled for revisions r0p0, r1p0, r1p1, and r1p2, and
335 CPU. This needs to be enabled for revisions r0p0, r1p0, r1p1 and r1p2 and
341 Cortex-A78AE CPU. This needs to be enabled for revisions r0p0 and r0p1.
345 Cortex-A78AE CPU. This needs to be enabled for revisions r0p0 and r0p1. This
349 Cortex-A78AE CPU. This needs to be enabled for revisions r0p0, r0p1 and r0p2.
353 Cortex-A78AE CPU. This needs to be enabled for revisions r0p0 and r0p1. This
357 Cortex-A78AE CPU. This erratum affects system configurations that do not use
364 Cortex-A78C CPU. This needs to be enabled for revision r0p0. The erratum is
368 Cortex-A78C CPU. This needs to be enabled for revision r0p0. The erratum is
372 Cortex-A78C CPU. This needs to be enabled for revisions r0p1, r0p2 and
376 Cortex-A78C CPU. This needs to be enabled for revisions r0p1, r0p2 and
380 Cortex-A78C CPU. This needs to be enabled for revisions r0p1 and r0p2. This
384 Cortex-A78C CPU. This needs to be enabled for revisions r0p1 and r0p2. This
388 Cortex-A78C CPU. This needs to be enabled for revisions r0p1 and r0p2. This
392 Cortex-A78C CPU, this erratum affects system configurations that do not use
397 Cortex-A78C CPU. This needs to be enabled for revisions r0p1 and r0p2.
401 Cortex-A78C CPU. This needs to be enabled for revisions r0p0, r0p1 and r0p2.
405 Cortex-A78C CPU. This needs to be enabled for revisions r0p1 and r0p2.
408 For Cortex-X1 CPU, the following errata build flags are defined:
411 CPU. This needs to be enabled only for revision <= r1p0 of the CPU.
414 CPU. This needs to be enabled only for revision <= r1p0 of the CPU.
417 CPU. This needs to be enabled only for revision <= r1p0 of the CPU.
422 CPU. This needs to be enabled only for revision r0p0 and r1p0 of the CPU.
425 CPU. This needs to be enabled only for revision <= r2p0 of the CPU.
428 CPU. This needs to be enabled only for revision <= r2p0 of the CPU.
431 CPU. This needs to be enabled only for revision <= r2p0 of the CPU.
434 CPU. This needs to be enabled only for revision <= r2p0 of the CPU.
437 CPU. This needs to be enabled only for revision <= r3p0 of the CPU.
440 CPU. This needs to be enabled only for revision <= r3p0 of the CPU.
443 CPU. This needs to be enabled only for revision <= r3p0 of the CPU.
446 CPU. This needs to be enabled only for revision <= r3p0 of the CPU.
449 CPU. This needs to be enabled only for revision <= r3p0 of the CPU.
452 CPU. This needs to be enabled only for revisions r3p0 - r4p0 of the CPU.
455 CPU. This needs to be enabled only for revision <= r4p0 of the CPU.
458 CPU. This needs to be enabled for revisions r3p0, r3p1, r4p0, and r4p1, for
462 CPU. This needs to be enabled for all revisions <= r4p1 of the CPU and is
468 CPU. This needs to be enabled for revision r0p0 of the CPU, it is fixed in
472 CPU. This needs to be enabled only for revisions r0p0 and r1p0, it is fixed
476 CPU. This needs to be enabled only for revisions r0p0 and r1p0, it is fixed
480 CPU. This needs to be enabled only for revisions r0p0 and r1p0, it is fixed
484 CPU. This needs to be enabled for r0p0, r1p0, and r1p1, it is still open.
487 CPU. This needs to be enabled only for revision r1p0 and r1p1 of the
488 CPU.
491 CPU. This needs to be enabled for revisions r1p0 and r1p1 of the CPU, the
496 CPU. This needs to be enabled for revisions r0p0, r1p0, and r1p1 of the
497 CPU. It is still open.
500 CPU. This needs to be enabled for revisions r0p0, r1p0, and r1p1 of the CPU.
504 CPU. This needs to be enabled for revisions r1p0 and r1p1 of the CPU, the
509 CPU. This needs to be enabled for revisions r0p0, r1p0, and r1p1 and r1p2 of
510 the CPU.
513 CPU. This needs to be enabled for revisions r0p0, r1p0 and r1p1 of the CPU.
517 CPU. This needs to be enabled for revisions r0p0, r1p0 and r1p1 of the CPU.
521 CPU, this erratum affects system configurations that do not use an ARM
526 CPU. This needs to be enabled for revisions r0p0, r1p0, r1p1 and r1p2 of the
527 CPU. It is still open.
530 CPU. This needs to be enabled for revisions r0p0, r1p0, r1p1, and r1p2 of the
531 CPU. It is still open.
534 CPU. This needs to be enabled for revisions r0p0, r1p0, r1p1, r1p2 of the
535 CPU. It is still open.
540 CPU. This needs to be enabled for revisions r0p0, r0p1 and r0p2. It is still
544 CPU. This needs to be enabled for revisions r0p0 and r0p1. It is fixed in
548 CPU. This needs to be enabled for revisions r0p0 and r0p1. It is fixed in
552 CPU, this affects system configurations that do not use and ARM interconnect
557 CPU. This needs to be enabled for revisions r0p0 and r0p1. It is fixed in
561 CPU. This needs to be enabled for revisions r0p0 and r0p1. It is fixed in
565 CPU. This needs to be enabled for revisions r0p0 and r0p1. It is fixed in
569 CPU, this affects all configurations. This needs to be enabled for revisions
575 Cortex-A710 CPU. This needs to be enabled only for revisions r0p0, r1p0 and
576 r2p0 of the CPU. It is still open.
579 Cortex-A710 CPU. This needs to be enabled only for revisions r0p0, r1p0 and
580 r2p0 of the CPU. It is still open.
583 Cortex-A710 CPU. This needs to be enabled for revisions r1p0, r2p0 of the CPU
587 Cortex-A710 CPU. This needs to be enabled for revisions r0p0, r1p0 and r2p0
588 of the CPU and is still open.
591 Cortex-A710 CPU. This needs to be enabled for revision r2p0 of the CPU and
595 Cortex-A710 CPU. This needs to be enabled for revisions r0p0, r1p0 and r2p0
596 and r2p1 of the CPU and is still open.
599 Cortex-A710 CPU. This needs to be enabled for revisions r0p0, r1p0 and r2p0
600 of the CPU and is fixed in r2p1.
603 Cortex-A710 CPU. This needs to be enabled for revisions r0p0, r1p0 and r2p0
604 of the CPU and is fixed in r2p1.
607 Cortex-A710 CPU. This needs to be enabled for revision r2p0 of the CPU
611 Cortex-A710 CPU. This needs to be enabled for revisions r0p0, r1p0 and r2p0
612 of the CPU and is fixed in r2p1.
615 Cortex-A710 CPU. This needs to be enabled for revisions r0p0, r1p0, r2p0 and
616 r2p1 of the CPU and is still open.
619 Cortex-A710 CPU. This needs to be enabled for revisions r0p0, r1p0 and r2p0
620 of the CPU and is fixed in r2p1.
623 Cortex-A710 CPU. This needs to be enabled for revisions r0p0, r1p0 and r2p0
624 of the CPU and is fixed in r2p1.
627 Cortex-A710 CPU. This needs to be enabled for revisions r0p0, r1p0 and r2p0
628 of the CPU and is fixed in r2p1.
631 CPU, and applies to system configurations that do not use and ARM
636 Cortex-A710 CPU. This needs to be enabled for revisions r0p0, r1p0, r2p0 and
637 r2p1 of the CPU and is still open.
640 Cortex-A710 CPU. This needs to be enabled for revisions r0p0, r1p0, r2p0 and
641 r2p1 of the CPU and is still open.
644 CPU. This needs to be enabled for revisions r0p0, r1p0, r2p0 and r2p1 of the
645 CPU and is still open.
650 CPU. This needs to be enabled for revision r0p0 of the CPU and is fixed in r0p1.
653 CPU. This needs to be enabled for revision r0p0 of the CPU and is fixed in r0p1.
656 CPU. This needs to be enabled for revision r0p0 of the CPU and is fixed in r0p1.
659 CPU. This needs to be enabled for revision r0p0 of the CPU and is fixed in r0p1.
662 CPU. This needs to be enabled for revision r0p0 of the CPU and is fixed in r0p1.
665 CPU. This needs to be enabled for revision r0p0 of the CPU and is fixed in r0p1.
668 CPU. This needs to be enabled for revisions r0p0, r0p1, r0p2, r0p3 and is still open.
671 CPU. This needs to be enabled for revision r0p0 of the CPU and is fixed in r0p1.
674 CPU. This needs to be enabled for revision r0p0 of the CPU and is fixed in r0p1.
677 CPU. This needs to be enabled for revision r0p0 of the CPU and is fixed in r0p1.
680 CPU. This needs to be enabled for revision r0p0 of the CPU and is fixed in r0p1.
683 CPU. This needs to be enabled for revision r0p0 of the CPU, it is fixed in
687 CPU. This needs to be enabled for revision r0p0 of the CPU, it is fixed in
691 CPU. This needs to be enabled for revisions r0p0, r0p1 and r0p2 of the CPU,
695 CPU. This needs to be enabled for revision r0p0, r0p1, r0p2, r0p3 and is still open.
698 CPU. This needs to be enabled for revision r0p0 of the CPU, it is fixed in
702 CPU. This needs to be enabled for revisions r0p0, r0p1 and r0p2. It is fixed
706 CPU. This needs to be enabled for revisions r0p0, r0p1 and r0p2. It is fixed
710 CPU, this erratum affects system configurations that do not use and ARM
715 CPU. This needs to be enabled for revisions r0p0, r0p1 and r0p2. It is fixed
721 CPU. This needs to be enabled for revisions r0p0, r1p0, and r2p0 of the CPU,
725 CPU. This needs to be enabled for revisions r0p0, r1p0, r2p0 and r2p1 of the CPU,
729 CPU. This needs to be enabled for revision r2p0 of the CPU, it is still open.
732 CPU. This needs to be enabled only for revisions r0p0, r1p0 and r2p0 of the
733 CPU, it is fixed in r2p1.
736 CPU. This needs to be enabled only for revisions r0p0, r1p0 and r2p0 of the
737 CPU, it is fixed in r2p1.
740 CPU. This needs to be enabled only for revisions r0p0, r1p0 and r2p0 of the
741 CPU, it is fixed in r2p1.
744 CPU. This needs to be enabled only for revision r2p0 of the CPU, it is fixed
748 CPU. This needs to be enabled for revisions r0p0, r1p0, r2p0 and r2p1 of the
749 CPU and is still open.
752 CPU. This needs to be enabled for revisions r0p0, r1p0 and r2p0 of the CPU
756 CPU and affects system configurations that do not use an ARM interconnect IP.
761 CPU. This needs to be enabled for revisions r0p0, r1p0, r2p0 and r2p1 of the
762 CPU and is still open.
765 CPU. This needs to be enabled for revisions r0p0, r1p0, r2p0 and r2p1 of the
766 CPU and is still open.
769 CPU. This needs to be enabled for revisions r0p0, r1p0, r2p0 and r2p1 of the
770 CPU and it is still open.
775 CPU. This needs to be enabled only for revisions r0p0, r1p0, r1p1 and r1p2 of
776 the CPU and is still open.
779 CPU. This needs to be enabled only for revisions r0p0 and r1p0 of the CPU, it
783 CPU. This needs to be enabled only for revisions r0p0, r1p0 and r1p1, it is
787 Cortex-X3 CPU. This needs to be enabled only for revisions r0p0 and r1p0
788 of the CPU, it is fixed in r1p1.
791 Cortex-X3 CPU. This needs to be enabled only for revisions r0p0 and r1p0
792 of the CPU, it is fixed in r1p1.
795 CPU. This needs to be enabled only for revisions r0p0, r1p0 and r1p1 of the
796 CPU, it is fixed in r1p2.
799 CPU. This needs to be enabled only for revisions r0p0 and r1p0 of the CPU.
803 CPU and affects system configurations that do not use an ARM interconnect
808 Cortex-X3 CPU. This needs to be enabled only for revisions r0p0, r1p0 and
812 CPU. This needs to be enabled only for revisions r0p0, r1p0 and r1p1. It is
816 CPU. This needs to be enabled only for revisions r0p0, r1p0 and r1p1 of the
817 CPU. It is fixed in r1p2.
822 CPU and affects system configurations that do not use an Arm interconnect IP.
830 CPU. This needs to be enabled for revisions r0p0 and r0p1. It is fixed
834 CPU. This needs to be enabled for revisions r0p0 and r0p1. It is fixed in r0p2.
839 Cortex-A510 CPU. This needs to be enabled only for revision r0p0, it is
843 Cortex-A510 CPU. This needs to be enabled only for revisions r0p0, r0p1,
847 Cortex-A510 CPU. This needs to be enabled only for revisions r0p0, r0p1 and
851 Cortex-A510 CPU. This needs to be enabled only for revision r0p2 and is fixed
856 Cortex-A510 CPU. This needs to be enabled only for revision r0p2 and is
861 Cortex-A510 CPU. This needs to be enabled for revisions r0p0, r0p1, r0p2,
866 Cortex-A510 CPU. This needs to be enabled for revisions r0p0, r0p1, r0p2,
870 Cortex-A510 CPU. This needs to be enabled for revisions r0p0, r0p1, r0p2,
874 Cortex-A510 CPU. This needs to be enabled for revisions r0p0, r0p1, r0p2,
878 Cortex-A510 CPU. This needs to applied for revisions r0p0, r0p1, r0p2,
882 Cortex-A510 CPU. This needs to applied for revisions r0p0, r0p1, r0p2,
886 Cortex-A510 CPU. This needs to be applied to revision r0p0, r0p1, r0p2,
892 Cortex-A520 CPU. This needs to applied for revisions r0p0, r0p1 of the
893 CPU and is still open.
896 Cortex-A520 CPU. This needs to be enabled for revisions r0p0 and r0p1.
902 Cortex-A715 CPU. This needs to be enabled for revisions r0p0 and r1p0.
906 Cortex-A715 CPU. This needs to be enabled for revisions r0p0 and r1p0. It is
910 Cortex-A715 CPU. This needs to be enabled only for revision r1p0 and
915 Cortex-A715 CPU. This needs to be enabled only for revision r1p0.
919 Cortex-A715 CPU. This needs to be enabled for revision r1p0. There is no
923 Cortex-A715 CPU. This needs to be enabled only for revision r1p0.
927 Cortex-A715 CPU. This needs to be enabled for revisions r0p0, r1p0
933 Cortex-A720 CPU. This needs to be enabled for revisions r0p0 and r0p1.
937 Cortex-A720 CPU. This needs to be enabled for revisions r0p0 and r0p1.
943 Similar to CPU errata, TF-A also implements workarounds for DSU (DynamIQ
952 of DSU errata workarounds are similar to `CPU errata workarounds`_.
973 CPU Specific optimizations
976 This section describes some of the optimizations allowed by the CPU micro
994 <= r0p3 of the CPU and is enabled by default.
998 enabled only for revisions <= r1p2 of the CPU and is enabled by default,