Lines Matching refs:hci_cmd_buffer
172 static void chipset_set_bd_addr_command(bd_addr_t addr, uint8_t *hci_cmd_buffer){ in chipset_set_bd_addr_command() argument
173 little_endian_store_16(hci_cmd_buffer, 0, OPCODE(OGF_VENDOR, 0x02)); in chipset_set_bd_addr_command()
174 hci_cmd_buffer[2] = 0x06; in chipset_set_bd_addr_command()
175 reverse_bd_addr(addr, &hci_cmd_buffer[3]); in chipset_set_bd_addr_command()
178 static void chipset_set_baudrate_command(uint32_t baudrate, uint8_t *hci_cmd_buffer){ in chipset_set_baudrate_command() argument
192 little_endian_store_16(hci_cmd_buffer, 0, OPCODE(OGF_VENDOR, 0x07)); in chipset_set_baudrate_command()
193 hci_cmd_buffer[2] = 0x01; in chipset_set_baudrate_command()
194 hci_cmd_buffer[3] = i; in chipset_set_baudrate_command()
205 static btstack_chipset_result_t chipset_next_command(uint8_t * hci_cmd_buffer){ in chipset_next_command() argument
211 little_endian_store_16(hci_cmd_buffer, 0, HCI_OPCODE_EM_CPU_RESET); in chipset_next_command()
212 hci_cmd_buffer[2] = 0; in chipset_next_command()
247 little_endian_store_16(hci_cmd_buffer, 0, HCI_OPCODE_EM_WRITE_PATCH_START); in chipset_next_command()
248 hci_cmd_buffer[2] = 5 + bytes_to_upload; in chipset_next_command()
249 hci_cmd_buffer[3] = 0; // upload to iRAM1 in chipset_next_command()
250 little_endian_store_32(hci_cmd_buffer, 4, crc); in chipset_next_command()
251 memcpy(&hci_cmd_buffer[8], &container_blob_data[container_blob_offset], bytes_to_upload); in chipset_next_command()
262 little_endian_store_16(hci_cmd_buffer, 0, HCI_OPCODE_EM_WRITE_PATCH_CONTINUE); in chipset_next_command()
263 hci_cmd_buffer[2] = 6 + bytes_to_upload; in chipset_next_command()
264 little_endian_store_16(hci_cmd_buffer, 3, patch_sequence_number++); in chipset_next_command()
265 little_endian_store_32(hci_cmd_buffer, 5, crc); in chipset_next_command()
266 memcpy(&hci_cmd_buffer[9], &container_blob_data[container_blob_offset], bytes_to_upload); in chipset_next_command()