Lines Matching refs:__ASM
52 __ASM volatile ("cpsie i" : : : "memory"); in __enable_irq()
63 __ASM volatile ("cpsid i" : : : "memory"); in __disable_irq()
77 __ASM volatile ("MRS %0, control" : "=r" (result) ); in __get_CONTROL()
90 __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); in __set_CONTROL()
104 __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); in __get_IPSR()
119 __ASM volatile ("MRS %0, apsr" : "=r" (result) ); in __get_APSR()
134 __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); in __get_xPSR()
149 __ASM volatile ("MRS %0, psp\n" : "=r" (result) ); in __get_PSP()
162 __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) : "sp"); in __set_PSP()
176 __ASM volatile ("MRS %0, msp\n" : "=r" (result) ); in __get_MSP()
189 __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) : "sp"); in __set_MSP()
203 __ASM volatile ("MRS %0, primask" : "=r" (result) ); in __get_PRIMASK()
216 __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); in __set_PRIMASK()
229 __ASM volatile ("cpsie f" : : : "memory"); in __enable_fault_irq()
240 __ASM volatile ("cpsid f" : : : "memory"); in __disable_fault_irq()
254 __ASM volatile ("MRS %0, basepri" : "=r" (result) ); in __get_BASEPRI()
267 __ASM volatile ("MSR basepri, %0" : : "r" (value) : "memory"); in __set_BASEPRI()
280 __ASM volatile ("MSR basepri_max, %0" : : "r" (value) : "memory"); in __set_BASEPRI_MAX()
294 __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); in __get_FAULTMASK()
307 __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); in __set_FAULTMASK()
327 __ASM volatile (""); in __get_FPSCR()
328 __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); in __get_FPSCR()
329 __ASM volatile (""); in __get_FPSCR()
347 __ASM volatile (""); in __set_FPSCR()
349 __ASM volatile (""); in __set_FPSCR()
383 __ASM volatile ("nop"); in __NOP()
394 __ASM volatile ("wfi"); in __WFI()
405 __ASM volatile ("wfe"); in __WFE()
415 __ASM volatile ("sev"); in __SEV()
427 __ASM volatile ("isb 0xF":::"memory"); in __ISB()
438 __ASM volatile ("dsb 0xF":::"memory"); in __DSB()
449 __ASM volatile ("dmb 0xF":::"memory"); in __DMB()
467 __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); in __REV()
484 __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); in __REV16()
503 __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); in __REVSH()
531 #define __BKPT(value) __ASM volatile ("bkpt "#value)
546 __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); in __RBIT()
587 __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) ); in __LDREXB()
592 __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); in __LDREXB()
610 __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) ); in __LDREXH()
615 __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); in __LDREXH()
632 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); in __LDREXW()
650 __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); in __STREXB()
668 __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); in __STREXH()
686 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); in __STREXW()
698 __ASM volatile ("clrex" ::: "memory"); in __CLREX()
713 __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
729 __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
746 __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); in __RRX()
763 __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*addr) ); in __LDRBT()
768 __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); in __LDRBT()
786 __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*addr) ); in __LDRHT()
791 __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); in __LDRHT()
808 __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*addr) ); in __LDRT()
822 __ASM volatile ("strbt %1, %0" : "=Q" (*addr) : "r" ((uint32_t)value) ); in __STRBT()
835 __ASM volatile ("strht %1, %0" : "=Q" (*addr) : "r" ((uint32_t)value) ); in __STRHT()
848 __ASM volatile ("strt %1, %0" : "=Q" (*addr) : "r" (value) ); in __STRT()
868 __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); in __SADD8()
876 __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); in __QADD8()
884 __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); in __SHADD8()
892 __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); in __UADD8()
900 __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); in __UQADD8()
908 __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); in __UHADD8()
917 __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); in __SSUB8()
925 __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); in __QSUB8()
933 __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); in __SHSUB8()
941 __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); in __USUB8()
949 __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); in __UQSUB8()
957 __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); in __UHSUB8()
966 __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); in __SADD16()
974 __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); in __QADD16()
982 __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); in __SHADD16()
990 __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); in __UADD16()
998 __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); in __UQADD16()
1006 __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); in __UHADD16()
1014 __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); in __SSUB16()
1022 __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); in __QSUB16()
1030 __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); in __SHSUB16()
1038 __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); in __USUB16()
1046 __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); in __UQSUB16()
1054 __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); in __UHSUB16()
1062 __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); in __SASX()
1070 __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); in __QASX()
1078 __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); in __SHASX()
1086 __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); in __UASX()
1094 __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); in __UQASX()
1102 __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); in __UHASX()
1110 __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); in __SSAX()
1118 __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); in __QSAX()
1126 __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); in __SHSAX()
1134 __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); in __USAX()
1142 __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); in __UQSAX()
1150 __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); in __UHSAX()
1158 __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); in __USAD8()
1166 __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); in __USADA8()
1173 __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
1180 __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
1188 __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); in __UXTB16()
1196 __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); in __UXTAB16()
1204 __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); in __SXTB16()
1212 __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); in __SXTAB16()
1220 __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); in __SMUAD()
1228 __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); in __SMUADX()
1236 __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); in __SMLAD()
1244 __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); in __SMLADX()
1257 …__ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op… in __SMLALD()
1259 …__ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op… in __SMLALD()
1274 …__ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (o… in __SMLALDX()
1276 …__ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (o… in __SMLALDX()
1286 __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); in __SMUSD()
1294 __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); in __SMUSDX()
1302 __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); in __SMLSD()
1310 __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); in __SMLSDX()
1323 …__ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op… in __SMLSLD()
1325 …__ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op… in __SMLSLD()
1340 …__ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (o… in __SMLSLDX()
1342 …__ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (o… in __SMLSLDX()
1352 __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); in __SEL()
1360 __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); in __QADD()
1368 __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); in __QSUB()
1375 __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
1383 __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \
1385 __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
1393 __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); in __SMMLA()