Lines Matching +full:image +full:- +full:specific

29        +----------+        +---------+
35        +----------+        +---------+
37        |   +------+        |   PSL   |
38        |   | CAPP |<------>|         |
39        +---+------+  PCIE  +---------+
48     (AFU). The AFU is used to implement specific functionality behind
66     - POWER8 and PSL Version 8 are compliant to the CAIA Version 1.0.
67     - POWER9 and PSL Version 9 are compliant to the CAIA Version 2.0.
92     applications may use the accelerator (although specific AFUs may
124     The WED is a 64-bit parameter passed to the AFU when a context is
158 	https://github.com/ibm-capi/libcxl
163 ----
175     and return -ENOSPC.
188 -----
221                 The Work Element Descriptor (WED) is a 64-bit argument
223                 address pointing to an AFU specific structure
250 ----
254     and contents of this area are specific to the particular AFU. The
264     Care should be taken when accessing MMIO space. Only 32 and 64-bit
266     with a specific endianness, so all MMIO accesses should consider
273 ----
276     (unless O_NONBLOCK is supplied). Returns -EIO in the case of an
403     card. The device is only used to write (flash) a new image on the
404     FPGA accelerator. Once the image is written and verified, the
406     image.
409 ----
415 -----
418     Starts and controls flashing a new FPGA image. Partial
419     reconfiguration is not supported (yet), so the image must contain
420     a copy of the PSL and AFU(s). Since an image can be quite large,
421     the caller may have to iterate, splitting the image in smaller
442         Pointer to a buffer with part of the image to write to the
449         Full size of the image.
457     described in Documentation/ABI/obsolete/sysfs-class-cxl
470 	                  KERNEL=="afu[0-9]*.[0-9]*s", SYMLINK="cxl/%b"