Lines Matching +full:sar2130p +full:- +full:gcc

1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,sar2130p-gcc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Global Clock & Reset Controller on sar2130p
10   - Dmitry Baryshkov <[email protected]>
14   power domains on sar2130p.
16   See also: include/dt-bindings/clock/qcom,sar2130p-gcc.h
20     const: qcom,sar2130p-gcc
24       - description: XO reference clock
25       - description: Sleep clock
26       - description: PCIe 0 pipe clock
27       - description: PCIe 1 pipe clock
28       - description: Primary USB3 PHY wrapper pipe clock
30   protected-clocks:
33   power-domains:
37   - compatible
38   - clocks
39   - '#power-domain-cells'
42   - $ref: qcom,gcc.yaml#
47   - |
48     #include <dt-bindings/clock/qcom,rpmh.h>
49     #include <dt-bindings/power/qcom,rpmhpd.h>
51     gcc: clock-controller@100000 {
52         compatible = "qcom,sar2130p-gcc";
59         power-domains = <&rpmhpd RPMHPD_CX>;
61         #clock-cells = <1>;
62         #reset-cells = <1>;
63         #power-domain-cells = <1>;