Lines Matching +full:region +full:- +full:unfreeze +full:- +full:timeout +full:- +full:us
1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/fpga/fpga-region.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: FPGA Region
10 - Michal Simek <[email protected]>
14 - Introduction
15 - Terminology
16 - Sequence
17 - FPGA Region
18 - Supported Use Models
19 - Constraints
46 Partial Reconfiguration Region (PRR)
53 into a PRR must fit and must use a subset of the region's connections.
54 * The busses within the FPGA are split such that each region gets its own
71 * During Partial Reconfiguration of a specific region, that region's bridge
89 ---------------- ----------------------------------
92 | ----| | ----------- -------- |
94 | | W | | | ----------- -------- |
96 | | B |<=====>|<==| ----------- -------- |
98 | | I | | | ----------- -------- |
100 | | G | | | ----------- -------- |
102 | ----| | ----------- -------- |
104 ---------------- ----------------------------------
107 region (PRR0-2) gets its own split of the busses that is independently gated by
108 a soft logic bridge (Bridge0-2) in the FPGA. The contents of each PRR can be
115 When a DT overlay that targets an FPGA Region is applied, the FPGA Region will
124 When the overlay is removed, the child nodes will be removed and the FPGA Region
128 FPGA Region
132 Region brings together the elements needed to program on a running system and
137 * image-specific information needed to the programming.
143 An FPGA Region that exists in the live Device Tree reflects the current state.
144 If the live tree shows a "firmware-name" property or child nodes under an FPGA
145 Region, the FPGA already has been programmed. A DTO that targets an FPGA Region
146 and adds the "firmware-name" property is taken as a request to reprogram the
150 The base FPGA Region in the device tree represents the FPGA and supports full
152 FPGA region will be the child of one of the hardware bridges (the bridge that
154 one bridge to control during FPGA programming, the region will also contain a
157 For partial reconfiguration (PR), each PR region will have an FPGA Region.
159 base FPGA region. The "Full Reconfiguration to add PRR's" example below shows
162 If an FPGA Region does not specify an FPGA Manager, it will inherit the FPGA
163 Manager specified by its ancestor FPGA Region. This supports both the case
165 a different FPGA Manager is used for each region.
169 region is getting reconfigured (see Figure 1 above). During PR, the FPGA's
178 a FPGA Region. The target of the Device Tree Overlay is the FPGA Region. Some
190 FPGA Region. The FPGA Region is the child of the bridge that allows
192 fpga-bridges property in the FPGA region or in the device tree overlay.
198 region while the buses are enabled for other sections. Before any partial
200 PRR's with FPGA bridges. The device tree should have an FPGA region for each
211 or region it is designed to go into.
217 --
218 [1] www.altera.com/content/dam/altera-www/global/en_US/pdfs/literature/ug/ug_partrecon.pdf
224 pattern: "^fpga-region(@.*|-([0-9]|[1-9][0-9]+))?$"
227 const: fpga-region
233 "#address-cells": true
234 "#size-cells": true
236 config-complete-timeout-us:
239 mode after the region has been programmed.
241 encrypted-fpga-config:
246 external-fpga-config:
251 firmware-name:
257 If this property is in an overlay targeting an FPGA region, it is
260 fpga-bridges:
261 $ref: /schemas/types.yaml#/definitions/phandle-array
266 If the fpga-region is the child of an fpga-bridge, the list should not
269 fpga-mgr:
273 inherit this property from their ancestor regions. An fpga-mgr property
274 in a region will override any inherited FPGA manager.
276 partial-fpga-config:
282 region-freeze-timeout-us:
285 become disabled before the region has been programmed.
287 region-unfreeze-timeout-us:
290 become enabled after the region has been programmed.
293 - compatible
294 - fpga-mgr
300 - |
304 fpga_region0: fpga-region@0 {
305 compatible = "fpga-region";
307 #address-cells = <1>;
308 #size-cells = <1>;
309 fpga-mgr = <&fpga_mgr0>;
313 firmware-name = "zynq-gpio.bin";
315 compatible = "xlnx,xps-gpio-1.00.a";
317 gpio-controller;
318 #gpio-cells = <2>;
322 - |
326 fpga_region1: fpga-region@0 {
327 compatible = "fpga-region";
330 #address-cells = <1>;
331 #size-cells = <1>;
332 fpga-mgr = <&fpga_mgr1>;
333 fpga-bridges = <&fpga_bridge1>;
334 partial-fpga-config;
337 firmware-name = "zynq-gpio-partial.bin";
339 compatible = "fixed-factor-clock";
341 #clock-cells = <0>;
342 clock-div = <2>;
343 clock-mult = <1>;
346 compatible = "simple-bus";
347 #address-cells = <1>;
348 #size-cells = <1>;
351 compatible = "xlnx,xps-gpio-1.00.a";
353 #gpio-cells = <2>;
354 gpio-controller;