Lines Matching +full:in +full:- +full:and +full:- +full:around

1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10   - Andrew Lunn <[email protected]>
11   - Florian Fainelli <[email protected]>
12   - Heiner Kallweit <[email protected]>
17   bus. These should follow the generic ethernet-phy.yaml document, or
22     pattern: '^mdio(-(bus|external))?(@.+|-([0-9]+))?$'
24   "#address-cells":
27   "#size-cells":
30   reset-gpios:
33       The phandle and specifier for the GPIO that controls the RESET
36   reset-delay-us:
38       RESET pulse width in microseconds. It applies to all MDIO devices
39       and must therefore be appropriately determined based on all devices
40       requirements (maximum value of all per-device RESET pulse widths).
42   reset-post-delay-us:
44       Delay after reset deassert in microseconds. It applies to all MDIO
45       devices and it's determined by how fast all devices are ready for
49   clock-frequency:
51       Desired MDIO bus clock frequency in Hz. Values greater than IEEE 802.3
55   suppress-preamble:
57       The 32 bit preamble should be suppressed. In order for this to
62   '@[0-9a-f]+$':
72       broken-turn-around:
76           the turn around line low at end of the control phase of the
79       reset-gpios:
82           The GPIO phandle and specifier for the MDIO reset signal.
84       reset-assert-us:
86           Delay after the reset was asserted in microseconds. If this
89       reset-deassert-us:
91           Delay after the reset was deasserted in microseconds. If
95       - reg
100   - |
103         #address-cells = <1>;
104         #size-cells = <0>;
106         reset-gpios = <&gpio2 5 1>;
107         reset-delay-us = <2>;
109         ethphy0: ethernet-phy@1 {
113         ethphy1: ethernet-phy@3 {