Lines Matching +full:a +full:- +full:display

4 Display Core Next (DCN)
7 To equip our readers with the basic knowledge of how AMD Display Core Next
9 you can see a picture that provides a DCN overview, keep in mind that this is a
12 .. kernel-figure:: dc_pipeline_overview.svg
17 * **Display Controller Hub (DCHUB)**: This is the gateway between the Scalable
21 * **Display Pipe and Plane (DPP)**: This block provides pre-blend pixel
26   multiple planes, using global or per-pixel alpha.
29   the display.
34 * **Display Output (DIO)**: Codify the output to the display connected to our
37 * **Display Writeback (DWB)**: It provides the ability to write the output of
38   the display pipe back to memory as video frames.
40 * **Multi-Media HUB (MMHUBBUB)**: Memory controller interface for DMCUB and DWB
45   the Display Micro-Controller Unit - version B (DMCUB), which is handled via
49   for all of the display controller clock domains.
54 every ASIC has variations around this base model. Notice that the display
56 the SDP as the element from our Data Fabric that feeds the display pipe.
61 want to drive an 8k@60Hz with a DSC enabled, our DCN may require 4 DPP and 2
63 specific scenario. Orchestrate all of these components together requires a
69 2. Global sync signals (green): It is a set of synchronization signals composed
78 All of these components are represented by a data structure named dc_state.
79 From DCHUB to MPC, we have a representation called dc_plane; from MPC to OPTC,
81 that HUBP accesses a surface using a specific format read from memory, and our
83 be sent to the display via dc_stream and dc_link.
86 ----------------------
88 Display pipeline can be broken down into two components that are usually
91 * DCHUB (Mainly referring to a subcomponent named HUBP)
101 OPP and OPTC are two joining blocks between FE and BE. On a side note, this is
102 a one-to-one mapping of the link encoder to PHY, but we can configure the DCN
104 is to change, blend and compose pixel data, while BE's job is to frame a
105 generic pixel stream to a specific display's pixel stream.
108 ---------
116 representation and convert them to a DCN specific floating-point format (i.e.,
117 different from the IEEE floating-point format). In the process, CNVC also
118 applies a degamma function to transform the data from non-linear to linear
119 space to relax the floating-point calculations following. Data would stay in
120 this floating-point format from DPP to OPP.
125 depth format), bit-depth reduction/dithering would kick in. In OPP, we would
126 also apply a regamma function to introduce the gamma removed earlier back.
130 ---------------------
135 pipeline** or **pipeline** or just **pipe** as an abstraction to indicate a
137 core treats DCN blocks as individual resources, meaning we can build a pipeline
139 In actuality, we can't connect an arbitrary block from one pipe to a block from
144 .. kernel-figure:: pipeline_4k_no_split.svg
146 Additionally, let's take a look at parts of the DTN log (see
147 'Documentation/gpu/amdgpu/display/dc-debug.rst' for more information) since
148 this log can help us to see part of this pipeline behavior in real-time::
162 we have just a single **pipeline** where the data flows from DCHUB to DIO, as
166 .. kernel-figure:: pipeline_4k_split.svg
180 From the above example, we now split the display pipeline into two vertical
181 parts of 1920x2160 (i.e., 3440x2160), and as a result, we could reduce the
184 that the pipe configuration can vary a lot according to the display
189 -----------
196 in order to support outputs that need a very high pixel clock, or for
205 calculated by the Display Mode Library - DML (drivers/gpu/drm/amd/display/dc/dml)
206 based on a large number of parameters and ensure our hardware is able to feed
217 Since DCN hardware is double-buffered the DC driver is able to program the
222 .. kernel-figure:: global_sync_vblank.svg
225 to a number of negative consequences, most of them quite catastrophic.
227 The following picture shows how global sync allows for a mailbox style of
228 updates, i.e. it allows for multiple re-configurations between VUpdate
232 .. kernel-figure:: config_example.svg