Lines Matching +full:display +full:- +full:interface

4 Display Core Next (DCN)
7 To equip our readers with the basic knowledge of how AMD Display Core Next
12 .. kernel-figure:: dc_pipeline_overview.svg
17 * **Display Controller Hub (DCHUB)**: This is the gateway between the Scalable
21 * **Display Pipe and Plane (DPP)**: This block provides pre-blend pixel
26   multiple planes, using global or per-pixel alpha.
29   the display.
34 * **Display Output (DIO)**: Codify the output to the display connected to our
37 * **Display Writeback (DWB)**: It provides the ability to write the output of
38   the display pipe back to memory as video frames.
40 * **Multi-Media HUB (MMHUBBUB)**: Memory controller interface for DMCUB and DWB
45   the Display Micro-Controller Unit - version B (DMCUB), which is handled via
49   for all of the display controller clock domains.
54 every ASIC has variations around this base model. Notice that the display
56 the SDP as the element from our Data Fabric that feeds the display pipe.
64 sophisticated communication interface which is highlighted in the diagram by
68 1. Pixel data interface (red): Represents the pixel data flow;
71 3. Config interface: Responsible to configure blocks;
83 be sent to the display via dc_stream and dc_link.
86 ----------------------
88 Display pipeline can be broken down into two components that are usually
102 a one-to-one mapping of the link encoder to PHY, but we can configure the DCN
105 generic pixel stream to a specific display's pixel stream.
108 ---------
116 representation and convert them to a DCN specific floating-point format (i.e.,
117 different from the IEEE floating-point format). In the process, CNVC also
118 applies a degamma function to transform the data from non-linear to linear
119 space to relax the floating-point calculations following. Data would stay in
120 this floating-point format from DPP to OPP.
125 depth format), bit-depth reduction/dithering would kick in. In OPP, we would
130 ---------------------
144 .. kernel-figure:: pipeline_4k_no_split.svg
147 'Documentation/gpu/amdgpu/display/dc-debug.rst' for more information) since
148 this log can help us to see part of this pipeline behavior in real-time::
166 .. kernel-figure:: pipeline_4k_split.svg
180 From the above example, we now split the display pipeline into two vertical
184 that the pipe configuration can vary a lot according to the display
189 -----------
205 calculated by the Display Mode Library - DML (drivers/gpu/drm/amd/display/dc/dml)
217 Since DCN hardware is double-buffered the DC driver is able to program the
222 .. kernel-figure:: global_sync_vblank.svg
228 updates, i.e. it allows for multiple re-configurations between VUpdate
232 .. kernel-figure:: config_example.svg