Lines Matching +full:0487 +full:a

11 Coresight CPU debug module is defined in ARMv8-a architecture reference manual
12 (ARM DDI 0487A.k) Chapter 'Part H: External debug', the CPU can integrate
43 - The driver supports a CPU running in either AArch64 or AArch32 mode. The
44   registers naming convention is a bit different between them, AArch64 uses
45   'ED' for register prefix (ARM DDI 0487A.k, chapter H9.1) and AArch32 uses
46   'DBG' as prefix (ARM DDI 0487A.k, chapter G5.1). The driver is unified to
49 - ARMv8-a (ARM DDI 0487A.k) and ARMv7-a (ARM DDI 0406C.b) have different
52   If PCSROffset=0b0000, on ARMv8-a the feature of EDPCSR is not implemented;
53   but ARMv7-a defines "PCSR samples are offset by a value that depends on the
54   instruction set state". For ARMv7-a, the driver checks furthermore if CPU
56   detailed description for offset is in ARMv7-a ARM (ARM DDI 0406C.b) chapter
59   If PCSROffset=0b0010, ARMv8-a defines "EDPCSR implemented, and samples have
70 have been enabled properly. In ARMv8-a ARM (ARM DDI 0487A.k) chapter 'H9.1
96 - On systems with a sane power controller which can behave correctly with
108   This means that even checking EDPRSR has the potential to cause a bus hang
112   is a recipe for disaster; so we need preventing CPU low power states at boot
136 uses the debugfs file system to provide a knob to dynamically enable or disable
139 To enable it, write a '1' into /sys/kernel/debug/coresight_cpu_debug/enable::
143 To disable it, write a '0' into /sys/kernel/debug/coresight_cpu_debug/enable::