Lines Matching +full:assigned +full:- +full:clocks
1 // SPDX-License-Identifier: GPL-2.0+
4 * Copyright 2017-2018 NXP
8 #include <dt-bindings/clock/imx7ulp-clock.h>
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #include "imx7ulp-pinfunc.h"
15 interrupt-parent = <&intc>;
17 #address-cells = <1>;
18 #size-cells = <1>;
37 #address-cells = <1>;
38 #size-cells = <0>;
41 compatible = "arm,cortex-a7";
47 intc: interrupt-controller@40021000 {
48 compatible = "arm,cortex-a7-gic";
49 #interrupt-cells = <3>;
50 interrupt-controller;
55 rosc: clock-rosc {
56 compatible = "fixed-clock";
57 clock-frequency = <32768>;
58 clock-output-names = "rosc";
59 #clock-cells = <0>;
62 sosc: clock-sosc {
63 compatible = "fixed-clock";
64 clock-frequency = <24000000>;
65 clock-output-names = "sosc";
66 #clock-cells = <0>;
69 sirc: clock-sirc {
70 compatible = "fixed-clock";
71 clock-frequency = <16000000>;
72 clock-output-names = "sirc";
73 #clock-cells = <0>;
76 firc: clock-firc {
77 compatible = "fixed-clock";
78 clock-frequency = <48000000>;
79 clock-output-names = "firc";
80 #clock-cells = <0>;
83 upll: clock-upll {
84 compatible = "fixed-clock";
85 clock-frequency = <480000000>;
86 clock-output-names = "upll";
87 #clock-cells = <0>;
91 compatible = "simple-bus";
92 #address-cells = <1>;
93 #size-cells = <1>;
97 edma1: dma-controller@40080000 {
98 #dma-cells = <2>;
99 compatible = "fsl,imx7ulp-edma";
102 dma-channels = <32>;
120 clock-names = "dma", "dmamux0";
121 clocks = <&pcc2 IMX7ULP_CLK_DMA1>,
126 compatible = "fsl,sec-v4.0";
127 #address-cells = <1>;
128 #size-cells = <1>;
131 clocks = <&pcc2 IMX7ULP_CLK_CAAM>,
133 clock-names = "aclk", "ipg";
136 compatible = "fsl,sec-v4.0-job-ring";
142 compatible = "fsl,sec-v4.0-job-ring";
149 compatible = "fsl,imx7ulp-lpuart";
152 clocks = <&pcc2 IMX7ULP_CLK_LPUART4>;
153 clock-names = "ipg";
154 assigned-clocks = <&pcc2 IMX7ULP_CLK_LPUART4>;
155 assigned-clock-parents = <&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>;
156 assigned-clock-rates = <24000000>;
161 compatible = "fsl,imx7ulp-lpuart";
164 clocks = <&pcc2 IMX7ULP_CLK_LPUART5>;
165 clock-names = "ipg";
166 assigned-clocks = <&pcc2 IMX7ULP_CLK_LPUART5>;
167 assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC>;
168 assigned-clock-rates = <48000000>;
173 compatible = "fsl,imx7ulp-pwm";
175 assigned-clocks = <&pcc2 IMX7ULP_CLK_LPTPM4>;
176 assigned-clock-parents = <&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>;
177 clocks = <&pcc2 IMX7ULP_CLK_LPTPM4>;
178 #pwm-cells = <3>;
183 compatible = "fsl,imx7ulp-tpm";
186 clocks = <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>,
188 clock-names = "ipg", "per";
192 compatible = "fsl,imx7ulp-usb", "fsl,imx6ul-usb", "fsl,imx27-usb";
195 clocks = <&pcc2 IMX7ULP_CLK_USB0>;
198 ahb-burst-config = <0x0>;
199 tx-burst-size-dword = <0x8>;
200 rx-burst-size-dword = <0x8>;
205 compatible = "fsl,imx7ulp-usbmisc", "fsl,imx7d-usbmisc",
206 "fsl,imx6q-usbmisc";
207 #index-cells = <1>;
211 usbphy1: usb-phy@40350000 {
212 compatible = "fsl,imx7ulp-usbphy";
215 clocks = <&pcc2 IMX7ULP_CLK_USB_PHY>;
216 #phy-cells = <0>;
221 compatible = "fsl,imx7ulp-usdhc";
224 clocks = <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>,
227 clock-names = "ipg", "ahb", "per";
228 bus-width = <4>;
229 fsl,tuning-start-tap = <20>;
230 fsl,tuning-step = <2>;
235 compatible = "fsl,imx7ulp-usdhc";
238 clocks = <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>,
241 clock-names = "ipg", "ahb", "per";
242 bus-width = <4>;
243 fsl,tuning-start-tap = <20>;
244 fsl,tuning-step = <2>;
248 scg1: clock-controller@403e0000 {
249 compatible = "fsl,imx7ulp-scg1";
251 clocks = <&rosc>, <&sosc>, <&sirc>,
253 clock-names = "rosc", "sosc", "sirc",
255 #clock-cells = <1>;
259 compatible = "fsl,imx7ulp-wdt";
262 clocks = <&pcc2 IMX7ULP_CLK_WDG1>;
263 assigned-clocks = <&pcc2 IMX7ULP_CLK_WDG1>;
264 assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC_BUS_CLK>;
265 timeout-sec = <40>;
268 pcc2: clock-controller@403f0000 {
269 compatible = "fsl,imx7ulp-pcc2";
271 #clock-cells = <1>;
272 clocks = <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>,
283 clock-names = "nic1_bus_clk", "nic1_clk", "ddr_clk",
287 assigned-clocks = <&pcc2 IMX7ULP_CLK_LPTPM5>;
288 assigned-clock-parents = <&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>;
291 smc1: clock-controller@40410000 {
292 compatible = "fsl,imx7ulp-smc1";
294 #clock-cells = <1>;
295 clocks = <&scg1 IMX7ULP_CLK_CORE_DIV>,
297 clock-names = "divcore", "hsrun_divcore";
300 pcc3: clock-controller@40b30000 {
301 compatible = "fsl,imx7ulp-pcc3";
303 #clock-cells = <1>;
304 clocks = <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>,
315 clock-names = "nic1_bus_clk", "nic1_clk", "ddr_clk",
323 compatible = "simple-bus";
324 #address-cells = <1>;
325 #size-cells = <1>;
330 compatible = "fsl,imx7ulp-lpi2c";
333 clocks = <&pcc3 IMX7ULP_CLK_LPI2C6>,
335 clock-names = "per", "ipg";
336 assigned-clocks = <&pcc3 IMX7ULP_CLK_LPI2C6>;
337 assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC>;
338 assigned-clock-rates = <48000000>;
343 compatible = "fsl,imx7ulp-lpi2c";
346 clocks = <&pcc3 IMX7ULP_CLK_LPI2C7>,
348 clock-names = "per", "ipg";
349 assigned-clocks = <&pcc3 IMX7ULP_CLK_LPI2C7>;
350 assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC>;
351 assigned-clock-rates = <48000000>;
356 compatible = "fsl,imx7ulp-lpuart";
359 clocks = <&pcc3 IMX7ULP_CLK_LPUART6>;
360 clock-names = "ipg";
361 assigned-clocks = <&pcc3 IMX7ULP_CLK_LPUART6>;
362 assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC>;
363 assigned-clock-rates = <48000000>;
368 compatible = "fsl,imx7ulp-lpuart";
371 clocks = <&pcc3 IMX7ULP_CLK_LPUART7>;
372 clock-names = "ipg";
373 assigned-clocks = <&pcc3 IMX7ULP_CLK_LPUART7>;
374 assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC>;
375 assigned-clock-rates = <48000000>;
379 memory-controller@40ab0000 {
380 compatible = "fsl,imx7ulp-mmdc", "fsl,imx6q-mmdc";
382 clocks = <&pcc3 IMX7ULP_CLK_MMDC>;
386 compatible = "fsl,imx7ulp-iomuxc1";
391 compatible = "fsl,imx7ulp-gpio", "fsl,vf610-gpio";
393 gpio-controller;
394 #gpio-cells = <2>;
396 interrupt-controller;
397 #interrupt-cells = <2>;
398 clocks = <&pcc2 IMX7ULP_CLK_RGPIO2P1>,
400 clock-names = "gpio", "port";
401 gpio-ranges = <&iomuxc1 0 0 20>;
405 compatible = "fsl,imx7ulp-gpio", "fsl,vf610-gpio";
407 gpio-controller;
408 #gpio-cells = <2>;
410 interrupt-controller;
411 #interrupt-cells = <2>;
412 clocks = <&pcc2 IMX7ULP_CLK_RGPIO2P1>,
414 clock-names = "gpio", "port";
415 gpio-ranges = <&iomuxc1 0 32 12>;
419 compatible = "fsl,imx7ulp-gpio", "fsl,vf610-gpio";
421 gpio-controller;
422 #gpio-cells = <2>;
424 interrupt-controller;
425 #interrupt-cells = <2>;
426 clocks = <&pcc2 IMX7ULP_CLK_RGPIO2P1>,
428 clock-names = "gpio", "port";
429 gpio-ranges = <&iomuxc1 0 64 16>;
433 compatible = "fsl,imx7ulp-gpio", "fsl,vf610-gpio";
435 gpio-controller;
436 #gpio-cells = <2>;
438 interrupt-controller;
439 #interrupt-cells = <2>;
440 clocks = <&pcc2 IMX7ULP_CLK_RGPIO2P1>,
442 clock-names = "gpio", "port";
443 gpio-ranges = <&iomuxc1 0 96 20>;
448 compatible = "simple-bus";
449 #address-cells = <1>;
450 #size-cells = <1>;
455 compatible = "fsl,imx7ulp-sim", "syscon";
460 compatible = "fsl,imx7ulp-ocotp", "syscon";
462 clocks = <&scg1 IMX7ULP_CLK_DUMMY>;
463 #address-cells = <1>;
464 #size-cells = <1>;