Lines Matching +full:assigned +full:- +full:clock +full:- +full:rates
1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/clock/imx8ulp-clock.h>
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/power/imx8ulp-power.h>
10 #include <dt-bindings/thermal/thermal.h>
12 #include "imx8ulp-pinfunc.h"
15 interrupt-parent = <&gic>;
16 #address-cells = <2>;
17 #size-cells = <2>;
36 #address-cells = <2>;
37 #size-cells = <0>;
41 compatible = "arm,cortex-a35";
43 enable-method = "psci";
44 next-level-cache = <&A35_L2>;
45 cpu-idle-states = <&cpu_sleep>;
50 compatible = "arm,cortex-a35";
52 enable-method = "psci";
53 next-level-cache = <&A35_L2>;
54 cpu-idle-states = <&cpu_sleep>;
57 A35_L2: l2-cache0 {
59 cache-level = <2>;
60 cache-unified;
63 idle-states {
64 entry-method = "psci";
66 cpu_sleep: cpu-sleep {
67 compatible = "arm,idle-state";
68 arm,psci-suspend-param = <0x0>;
69 local-timer-stop;
70 entry-latency-us = <1000>;
71 exit-latency-us = <700>;
72 min-residency-us = <2700>;
77 gic: interrupt-controller@2d400000 {
78 compatible = "arm,gic-v3";
81 #interrupt-cells = <3>;
82 interrupt-controller;
87 compatible = "arm,cortex-a35-pmu";
88 interrupt-parent = <&gic>;
91 interrupt-affinity = <&A35_0>, <&A35_1>;
95 compatible = "arm,psci-1.0";
99 thermal-zones {
100 cpu-thermal {
101 polling-delay-passive = <250>;
102 polling-delay = <2000>;
103 thermal-sensors = <&scmi_sensor 0>;
122 compatible = "arm,armv8-timer";
124 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* Physical Non-Secure */
129 frosc: clock-frosc {
130 compatible = "fixed-clock";
131 clock-frequency = <192000000>;
132 clock-output-names = "frosc";
133 #clock-cells = <0>;
136 lposc: clock-lposc {
137 compatible = "fixed-clock";
138 clock-frequency = <1000000>;
139 clock-output-names = "lposc";
140 #clock-cells = <0>;
143 rosc: clock-rosc {
144 compatible = "fixed-clock";
145 clock-frequency = <32768>;
146 clock-output-names = "rosc";
147 #clock-cells = <0>;
150 sosc: clock-sosc {
151 compatible = "fixed-clock";
152 clock-frequency = <24000000>;
153 clock-output-names = "sosc";
154 #clock-cells = <0>;
158 compatible = "mmio-sram";
161 #address-cells = <1>;
162 #size-cells = <1>;
165 scmi_buf: scmi-sram-section@0 {
166 compatible = "arm,scmi-shmem";
173 compatible = "arm,scmi-smc";
174 arm,smc-id = <0xc20000fe>;
175 #address-cells = <1>;
176 #size-cells = <0>;
181 #power-domain-cells = <1>;
186 #thermal-sensor-cells = <1>;
191 cm33: remoteproc-cm33 {
192 compatible = "fsl,imx8ulp-cm33";
197 compatible = "simple-bus";
198 #address-cells = <1>;
199 #size-cells = <1>;
204 compatible = "fsl,imx8ulp-mu-s4";
207 #mbox-cells = <2>;
211 compatible = "simple-bus";
213 #address-cells = <1>;
214 #size-cells = <1>;
217 edma1: dma-controller@29010000 {
218 compatible = "fsl,imx8ulp-edma";
220 #dma-cells = <3>;
221 dma-channels = <32>;
271 clock-names = "dma", "ch00","ch01", "ch02", "ch03",
282 compatible = "fsl,imx8ulp-mu";
285 #mbox-cells = <2>;
290 compatible = "fsl,imx8ulp-mu";
294 #mbox-cells = <2>;
299 compatible = "fsl,imx8ulp-wdt", "fsl,imx7ulp-wdt";
303 assigned-clocks = <&pcc3 IMX8ULP_CLK_WDOG3>;
304 assigned-clock-parents = <&cgc1 IMX8ULP_CLK_SOSC_DIV2>;
305 timeout-sec = <40>;
308 cgc1: clock-controller@292c0000 {
309 compatible = "fsl,imx8ulp-cgc1";
311 #clock-cells = <1>;
314 pcc3: clock-controller@292d0000 {
315 compatible = "fsl,imx8ulp-pcc3";
317 #clock-cells = <1>;
318 #reset-cells = <1>;
322 compatible = "fsl,sec-v4.0";
325 #address-cells = <1>;
326 #size-cells = <1>;
329 compatible = "fsl,sec-v4.0-job-ring";
335 compatible = "fsl,sec-v4.0-job-ring";
341 compatible = "fsl,sec-v4.0-job-ring";
347 compatible = "fsl,sec-v4.0-job-ring";
354 compatible = "fsl,imx8ulp-tpm", "fsl,imx7ulp-tpm";
359 clock-names = "ipg", "per";
364 compatible = "fsl,imx8ulp-lpi2c", "fsl,imx7ulp-lpi2c";
369 clock-names = "per", "ipg";
370 assigned-clocks = <&pcc3 IMX8ULP_CLK_LPI2C4>;
371 assigned-clock-parents = <&cgc1 IMX8ULP_CLK_FROSC_DIV2>;
372 assigned-clock-rates = <48000000>;
377 compatible = "fsl,imx8ulp-lpi2c", "fsl,imx7ulp-lpi2c";
382 clock-names = "per", "ipg";
383 assigned-clocks = <&pcc3 IMX8ULP_CLK_LPI2C5>;
384 assigned-clock-parents = <&cgc1 IMX8ULP_CLK_FROSC_DIV2>;
385 assigned-clock-rates = <48000000>;
390 compatible = "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart";
394 clock-names = "ipg";
399 compatible = "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart";
403 clock-names = "ipg";
408 #address-cells = <1>;
409 #size-cells = <0>;
410 compatible = "fsl,imx8ulp-spi", "fsl,imx7ulp-spi";
415 clock-names = "per", "ipg";
416 assigned-clocks = <&pcc3 IMX8ULP_CLK_LPSPI4>;
417 assigned-clock-parents = <&cgc1 IMX8ULP_CLK_FROSC_DIV2>;
418 assigned-clock-rates = <48000000>;
423 #address-cells = <1>;
424 #size-cells = <0>;
425 compatible = "fsl,imx8ulp-spi", "fsl,imx7ulp-spi";
430 clock-names = "per", "ipg";
431 assigned-clocks = <&pcc3 IMX8ULP_CLK_LPSPI5>;
432 assigned-clock-parents = <&cgc1 IMX8ULP_CLK_FROSC_DIV2>;
433 assigned-clock-rates = <48000000>;
439 compatible = "simple-bus";
441 #address-cells = <1>;
442 #size-cells = <1>;
445 pcc4: clock-controller@29800000 {
446 compatible = "fsl,imx8ulp-pcc4";
448 #clock-cells = <1>;
449 #reset-cells = <1>;
453 compatible = "nxp,imx8ulp-fspi";
455 reg-names = "fspi_base", "fspi_mmap";
456 #address-cells = <1>;
457 #size-cells = <0>;
461 clock-names = "fspi_en", "fspi";
462 assigned-clocks = <&pcc4 IMX8ULP_CLK_FLEXSPI2>;
463 assigned-clock-parents = <&cgc1 IMX8ULP_CLK_SPLL3_PFD3_DIV2>;
468 compatible = "fsl,imx8ulp-lpi2c", "fsl,imx7ulp-lpi2c";
473 clock-names = "per", "ipg";
474 assigned-clocks = <&pcc4 IMX8ULP_CLK_LPI2C6>;
475 assigned-clock-parents = <&cgc1 IMX8ULP_CLK_FROSC_DIV2>;
476 assigned-clock-rates = <48000000>;
481 compatible = "fsl,imx8ulp-lpi2c", "fsl,imx7ulp-lpi2c";
486 clock-names = "per", "ipg";
487 assigned-clocks = <&pcc4 IMX8ULP_CLK_LPI2C7>;
488 assigned-clock-parents = <&cgc1 IMX8ULP_CLK_FROSC_DIV2>;
489 assigned-clock-rates = <48000000>;
494 compatible = "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart";
498 clock-names = "ipg";
503 compatible = "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart";
507 clock-names = "ipg";
512 compatible = "fsl,imx8ulp-sai";
518 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
520 dma-names = "rx", "tx";
521 #sound-dai-cells = <0>;
527 compatible = "fsl,imx8ulp-sai";
533 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
535 dma-names = "rx", "tx";
536 #sound-dai-cells = <0>;
542 compatible = "fsl,imx8ulp-iomuxc1";
547 compatible = "fsl,imx8ulp-usdhc", "fsl,imx8mm-usdhc";
553 clock-names = "ipg", "ahb", "per";
554 power-domains = <&scmi_devpd IMX8ULP_PD_USDHC0>;
555 assigned-clocks = <&cgc1 IMX8ULP_CLK_SPLL3_PFD3_DIV1>,
557 assigned-clock-parents = <0>, <&cgc1 IMX8ULP_CLK_SPLL3_PFD3_DIV1>;
558 assigned-clock-rates = <389283840>, <389283840>;
559 fsl,tuning-start-tap = <20>;
560 fsl,tuning-step = <2>;
561 bus-width = <4>;
566 compatible = "fsl,imx8ulp-usdhc", "fsl,imx8mm-usdhc";
572 clock-names = "ipg", "ahb", "per";
573 power-domains = <&scmi_devpd IMX8ULP_PD_USDHC1>;
574 assigned-clocks = <&cgc1 IMX8ULP_CLK_SPLL3_PFD3_DIV2>,
576 assigned-clock-parents = <0>, <&cgc1 IMX8ULP_CLK_SPLL3_PFD3_DIV2>;
577 assigned-clock-rates = <194641920>, <194641920>;
578 fsl,tuning-start-tap = <20>;
579 fsl,tuning-step = <2>;
580 bus-width = <4>;
585 compatible = "fsl,imx8ulp-usdhc", "fsl,imx8mm-usdhc";
591 clock-names = "ipg", "ahb", "per";
592 power-domains = <&scmi_devpd IMX8ULP_PD_USDHC2_USB1>;
593 assigned-clocks = <&cgc1 IMX8ULP_CLK_SPLL3_PFD3_DIV2>,
595 assigned-clock-parents = <0>, <&cgc1 IMX8ULP_CLK_SPLL3_PFD3_DIV2>;
596 assigned-clock-rates = <194641920>, <194641920>;
597 fsl,tuning-start-tap = <20>;
598 fsl,tuning-step = <2>;
599 bus-width = <4>;
604 compatible = "fsl,imx8ulp-usb", "fsl,imx7ulp-usb", "fsl,imx6ul-usb";
608 power-domains = <&scmi_devpd IMX8ULP_PD_USB0>;
611 ahb-burst-config = <0x0>;
612 tx-burst-size-dword = <0x8>;
613 rx-burst-size-dword = <0x8>;
618 compatible = "fsl,imx8ulp-usbmisc", "fsl,imx7d-usbmisc",
619 "fsl,imx6q-usbmisc";
621 #index-cells = <1>;
625 usbphy1: usb-phy@29910000 {
626 compatible = "fsl,imx8ulp-usbphy", "fsl,imx7ulp-usbphy";
630 #phy-cells = <0>;
635 compatible = "fsl,imx8ulp-usb", "fsl,imx7ulp-usb", "fsl,imx6ul-usb";
639 power-domains = <&scmi_devpd IMX8ULP_PD_USDHC2_USB1>;
642 ahb-burst-config = <0x0>;
643 tx-burst-size-dword = <0x8>;
644 rx-burst-size-dword = <0x8>;
649 compatible = "fsl,imx8ulp-usbmisc", "fsl,imx7d-usbmisc",
650 "fsl,imx6q-usbmisc";
652 #index-cells = <1>;
656 usbphy2: usb-phy@29930000 {
657 compatible = "fsl,imx8ulp-usbphy", "fsl,imx7ulp-usbphy";
661 #phy-cells = <0>;
666 compatible = "fsl,imx8ulp-fec", "fsl,imx6ul-fec", "fsl,imx6q-fec";
669 interrupt-names = "int0";
670 fsl,num-tx-queues = <1>;
671 fsl,num-rx-queues = <1>;
677 compatible = "fsl,imx8ulp-gpio";
679 gpio-controller;
680 #gpio-cells = <2>;
683 interrupt-controller;
684 #interrupt-cells = <2>;
687 clock-names = "gpio", "port";
688 gpio-ranges = <&iomuxc1 0 32 24>;
692 compatible = "fsl,imx8ulp-gpio";
694 gpio-controller;
695 #gpio-cells = <2>;
698 interrupt-controller;
699 #interrupt-cells = <2>;
702 clock-names = "gpio", "port";
703 gpio-ranges = <&iomuxc1 0 64 32>;
707 compatible = "simple-bus";
709 #address-cells = <1>;
710 #size-cells = <1>;
713 edma2: dma-controller@2d800000 {
714 compatible = "fsl,imx8ulp-edma";
716 #dma-cells = <3>;
717 dma-channels = <32>;
767 clock-names = "dma", "ch00","ch01", "ch02", "ch03",
777 cgc2: clock-controller@2da60000 {
778 compatible = "fsl,imx8ulp-cgc2";
780 #clock-cells = <1>;
783 pcc5: clock-controller@2da70000 {
784 compatible = "fsl,imx8ulp-pcc5";
786 #clock-cells = <1>;
787 #reset-cells = <1>;
791 compatible = "fsl,imx8ulp-sai";
797 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
799 dma-names = "rx", "tx";
800 #sound-dai-cells = <0>;
806 compatible = "fsl,imx8ulp-sai";
812 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
814 dma-names = "rx", "tx";
815 #sound-dai-cells = <0>;
821 compatible = "fsl,imx8ulp-spdif";
834 clock-names = "core", "rxtx0",
840 dma-names = "rx", "tx";
846 compatible = "fsl,imx8ulp-gpio";
848 gpio-controller;
849 #gpio-cells = <2>;
852 interrupt-controller;
853 #interrupt-cells = <2>;
856 clock-names = "gpio", "port";
857 gpio-ranges = <&iomuxc1 0 0 24>;