Lines Matching +full:fifo +full:- +full:depth
1 // SPDX-License-Identifier: GPL-2.0
6 /dts-v1/;
7 #include <dt-bindings/reset/altr,rst-mgr-s10.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/clock/agilex-clock.h>
13 compatible = "intel,socfpga-agilex";
14 #address-cells = <2>;
15 #size-cells = <2>;
17 reserved-memory {
18 #address-cells = <2>;
19 #size-cells = <2>;
23 compatible = "shared-dma-pool";
26 no-map;
31 #address-cells = <1>;
32 #size-cells = <0>;
35 compatible = "arm,cortex-a53";
37 enable-method = "psci";
42 compatible = "arm,cortex-a53";
44 enable-method = "psci";
49 compatible = "arm,cortex-a53";
51 enable-method = "psci";
56 compatible = "arm,cortex-a53";
58 enable-method = "psci";
65 compatible = "intel,agilex-svc";
67 memory-region = <&service_reserved>;
69 fpga_mgr: fpga-mgr {
70 compatible = "intel,agilex-soc-fpga-mgr";
75 fpga-region {
76 compatible = "fpga-region";
77 #address-cells = <0x2>;
78 #size-cells = <0x2>;
79 fpga-mgr = <&fpga_mgr>;
83 compatible = "arm,cortex-a53-pmu";
88 interrupt-affinity = <&cpu0>,
92 interrupt-parent = <&intc>;
96 compatible = "arm,psci-0.2";
100 intc: interrupt-controller@fffc1000 {
101 compatible = "arm,gic-400", "arm,cortex-a15-gic";
102 #interrupt-cells = <3>;
103 interrupt-controller;
104 interrupt-parent = <&intc>;
114 cb_intosc_hs_div2_clk: cb-intosc-hs-div2-clk {
115 #clock-cells = <0>;
116 compatible = "fixed-clock";
119 cb_intosc_ls_clk: cb-intosc-ls-clk {
120 #clock-cells = <0>;
121 compatible = "fixed-clock";
124 f2s_free_clk: f2s-free-clk {
125 #clock-cells = <0>;
126 compatible = "fixed-clock";
130 #clock-cells = <0>;
131 compatible = "fixed-clock";
134 qspi_clk: qspi-clk {
135 #clock-cells = <0>;
136 compatible = "fixed-clock";
137 clock-frequency = <200000000>;
142 compatible = "arm,armv8-timer";
143 interrupt-parent = <&intc>;
151 #phy-cells = <0>;
152 compatible = "usb-nop-xceiv";
156 #address-cells = <1>;
157 #size-cells = <1>;
158 compatible = "simple-bus";
160 interrupt-parent = <&intc>;
163 clkmgr: clock-controller@ffd10000 {
164 compatible = "intel,agilex-clkmgr";
166 #clock-cells = <1>;
170 compatible = "altr,socfpga-stmmac-a10-s10", "snps,dwmac-3.74a", "snps,dwmac";
173 interrupt-names = "macirq";
174 mac-address = [00 00 00 00 00 00];
176 reset-names = "stmmaceth", "ahb";
177 tx-fifo-depth = <16384>;
178 rx-fifo-depth = <16384>;
179 snps,multicast-filter-bins = <256>;
181 altr,sysmgr-syscon = <&sysmgr 0x44 0>;
183 clock-names = "stmmaceth", "ptp_ref";
188 compatible = "altr,socfpga-stmmac-a10-s10", "snps,dwmac-3.74a", "snps,dwmac";
191 interrupt-names = "macirq";
192 mac-address = [00 00 00 00 00 00];
194 reset-names = "stmmaceth", "ahb";
195 tx-fifo-depth = <16384>;
196 rx-fifo-depth = <16384>;
197 snps,multicast-filter-bins = <256>;
199 altr,sysmgr-syscon = <&sysmgr 0x48 0>;
201 clock-names = "stmmaceth", "ptp_ref";
206 compatible = "altr,socfpga-stmmac-a10-s10", "snps,dwmac-3.74a", "snps,dwmac";
209 interrupt-names = "macirq";
210 mac-address = [00 00 00 00 00 00];
212 reset-names = "stmmaceth", "ahb";
213 tx-fifo-depth = <16384>;
214 rx-fifo-depth = <16384>;
215 snps,multicast-filter-bins = <256>;
217 altr,sysmgr-syscon = <&sysmgr 0x4c 0>;
219 clock-names = "stmmaceth", "ptp_ref";
224 #address-cells = <1>;
225 #size-cells = <0>;
226 compatible = "snps,dw-apb-gpio";
231 porta: gpio-controller@0 {
232 compatible = "snps,dw-apb-gpio-port";
233 gpio-controller;
234 #gpio-cells = <2>;
235 snps,nr-gpios = <24>;
237 interrupt-controller;
238 #interrupt-cells = <2>;
244 #address-cells = <1>;
245 #size-cells = <0>;
246 compatible = "snps,dw-apb-gpio";
251 portb: gpio-controller@0 {
252 compatible = "snps,dw-apb-gpio-port";
253 gpio-controller;
254 #gpio-cells = <2>;
255 snps,nr-gpios = <24>;
257 interrupt-controller;
258 #interrupt-cells = <2>;
264 #address-cells = <1>;
265 #size-cells = <0>;
266 compatible = "snps,designware-i2c";
275 #address-cells = <1>;
276 #size-cells = <0>;
277 compatible = "snps,designware-i2c";
286 #address-cells = <1>;
287 #size-cells = <0>;
288 compatible = "snps,designware-i2c";
297 #address-cells = <1>;
298 #size-cells = <0>;
299 compatible = "snps,designware-i2c";
308 #address-cells = <1>;
309 #size-cells = <0>;
310 compatible = "snps,designware-i2c";
319 #address-cells = <1>;
320 #size-cells = <0>;
321 compatible = "altr,socfpga-dw-mshc";
324 fifo-depth = <0x400>;
326 reset-names = "reset";
329 clock-names = "biu", "ciu";
331 altr,sysmgr-syscon = <&sysmgr 0x28 4>;
335 nand: nand-controller@ffb90000 {
336 #address-cells = <1>;
337 #size-cells = <0>;
338 compatible = "altr,socfpga-denali-nand";
341 reg-names = "nand_data", "denali_reg";
346 clock-names = "nand", "nand_x", "ecc";
352 compatible = "mmio-sram";
354 #address-cells = <1>;
355 #size-cells = <1>;
359 pdma: dma-controller@ffda0000 {
371 #dma-cells = <1>;
373 reset-names = "dma", "dma-ocp";
375 clock-names = "apb_pclk";
379 compatible = "pinctrl-single";
380 #pinctrl-cells = <1>;
382 pinctrl-single,register-width = <32>;
383 pinctrl-single,function-mask = <0x0000000f>;
387 compatible = "pinctrl-single";
388 #pinctrl-cells = <1>;
390 pinctrl-single,register-width = <32>;
394 compatible = "altr,stratix10-rst-mgr", "altr,rst-mgr";
396 #reset-cells = <1>;
400 compatible = "arm,mmu-500", "arm,smmu-v2";
402 #global-interrupts = <2>;
403 #iommu-cells = <1>;
404 interrupt-parent = <&intc>;
407 /* Global Non-secure Fault */
409 /* Non-secure Context Interrupts (32) */
442 stream-match-mask = <0x7ff0>;
450 compatible = "snps,dw-apb-ssi";
451 #address-cells = <1>;
452 #size-cells = <0>;
456 reset-names = "spi";
457 reg-io-width = <4>;
458 num-cs = <4>;
464 compatible = "snps,dw-apb-ssi";
465 #address-cells = <1>;
466 #size-cells = <0>;
470 reset-names = "spi";
471 reg-io-width = <4>;
472 num-cs = <4>;
478 compatible = "altr,sys-mgr-s10","altr,sys-mgr";
483 compatible = "snps,dw-apb-timer";
487 clock-names = "timer";
491 compatible = "snps,dw-apb-timer";
495 clock-names = "timer";
499 compatible = "snps,dw-apb-timer";
503 clock-names = "timer";
507 compatible = "snps,dw-apb-timer";
511 clock-names = "timer";
515 compatible = "snps,dw-apb-uart";
518 reg-shift = <2>;
519 reg-io-width = <4>;
526 compatible = "snps,dw-apb-uart";
529 reg-shift = <2>;
530 reg-io-width = <4>;
537 compatible = "intel,socfpga-agilex-hsotg", "snps,dwc2";
541 phy-names = "usb2-phy";
543 reset-names = "dwc2", "dwc2-ecc";
545 clock-names = "otg";
551 compatible = "intel,socfpga-agilex-hsotg", "snps,dwc2";
555 phy-names = "usb2-phy";
557 reset-names = "dwc2", "dwc2-ecc";
564 compatible = "snps,dw-wdt";
573 compatible = "snps,dw-wdt";
582 compatible = "snps,dw-wdt";
591 compatible = "snps,dw-wdt";
600 compatible = "altr,sdr-ctl", "syscon";
605 compatible = "altr,socfpga-s10-ecc-manager",
606 "altr,socfpga-a10-ecc-manager";
607 altr,sysmgr-syscon = <&sysmgr>;
608 #address-cells = <1>;
609 #size-cells = <1>;
611 interrupt-controller;
612 #interrupt-cells = <2>;
616 compatible = "altr,sdram-edac-s10";
617 altr,sdr-syscon = <&sdr>;
621 ocram-ecc@ff8cc000 {
622 compatible = "altr,socfpga-s10-ocram-ecc",
623 "altr,socfpga-a10-ocram-ecc";
625 altr,ecc-parent = <&ocram>;
629 usb0-ecc@ff8c4000 {
630 compatible = "altr,socfpga-s10-usb-ecc",
631 "altr,socfpga-usb-ecc";
633 altr,ecc-parent = <&usb0>;
637 emac0-rx-ecc@ff8c0000 {
638 compatible = "altr,socfpga-s10-eth-mac-ecc",
639 "altr,socfpga-eth-mac-ecc";
641 altr,ecc-parent = <&gmac0>;
645 emac0-tx-ecc@ff8c0400 {
646 compatible = "altr,socfpga-s10-eth-mac-ecc",
647 "altr,socfpga-eth-mac-ecc";
649 altr,ecc-parent = <&gmac0>;
653 sdmmca-ecc@ff8c8c00 {
654 compatible = "altr,socfpga-s10-sdmmc-ecc",
655 "altr,socfpga-sdmmc-ecc";
657 altr,ecc-parent = <&mmc>;
664 compatible = "intel,socfpga-qspi", "cdns,qspi-nor";
665 #address-cells = <1>;
666 #size-cells = <0>;
670 cdns,fifo-depth = <128>;
671 cdns,fifo-width = <4>;
672 cdns,trigger-address = <0x00000000>;