Lines Matching +full:0487 +full:a

30 	 * Provide a wxN alias for each wN register so what we can paste a xN
31 	 * reference after a 'w' to obtain the 32-bit version.
58 	isb	// Take effect before a subsequent clear of DAIF.D
150  * Define a macro that constructs a 64-bit value by concatenating two
178 	 * @tmp: optional 64-bit scratch register to be used if <dst> is a
365  * Macro to perform a data cache maintenance for the interval
406  * Macro to perform a data cache maintenance for the interval
445  * load_ttbr1 - install @pgtbl as a TTBR1 page table
458  * in the tlb, switch the ttbr to a zero page when we invalidate the old
459  * records. D4.7.1 'General TLB maintenance requirements' in ARM DDI 0487A.i
460  * Even switching to our copied tables will cause a changed output address at
514  * Annotate a function as being unsuitable for kprobes.
532 	 * Emit a 64-bit absolute little endian symbol reference in a way that
533 	 * ensures that it will be resolved at build time, even when building a
543 	 * mov_q - move an immediate constant into a 64-bit register using
576  * additional paging level, and on LPA2/16k pages, we would end up with a root
595  * Arrange a physical address in a TTBR register, taking care of 52-bit
640  * to executing the MSR that will change SCTLR_ELn[M] from a value of 1 to 0.
682 	.error		"extra should be a multiple of 16 bytes"
748 	 * If we are serving a softirq, there is no point in yielding: the
769  * This macro emits a program property note section identifying
788 	.pushsection .note.gnu.property, "a"
802 	 * clang and GCC) treat this as a 32 bit value so no swizzling