Lines Matching +full:0487 +full:a

89  * AMO:		Override CPSR.A and enable signaling with VA
93  * PTW:		Take a stage2 fault if a stage1 walk steps in device memory
152  * 40 bits wide (T0SZ = 24).  Systems with a PARange smaller than 40 bits are
168  * See D.10.2.121, VTCR_EL2, in ARM DDI 0487C.a
186  * Where TGRAN_SL0_BASE is a magic number depending on the page size:
223  * descriptors in section D4.2.8 in ARM DDI 0487C.a.
228  * algorithm determines the alignment of a table base address at a given
232  * depending on the T0SZ, the value of "x" is defined based on a
233  * Magic constant for a given PAGE_SIZE and Entry Level. The
255  * We have a magic formula for the Magic_N below:
282  * levels for a given IPA size (which we do, see stage2_pt_levels())
318  * RES0 and polarity masks as of DDI0487J.a, to be updated as needed.
320  * the published ARM ARM, which we use as a reference.
322  * Once we get to a point where the two describe the same thing, we'll
330  * The HFGWTR bits are a subset of HFGRTR bits. To ensure we don't miss any