Lines Matching +full:compare +full:- +full:and +full:- +full:swap
3 M68000 Hi-Performance Microprocessor Division
5 Production Release P1.00 -- October 10, 1994
9 THE SOFTWARE is provided on an "AS IS" basis and without warranty.
13 and any warranty against infringement with regard to the SOFTWARE label
14 (INCLUDING ANY MODIFIED VERSIONS THEREOF) and any accompanying written materials.
21 Motorola assumes no responsibility for the maintenance and support of the SOFTWARE.
23 You are hereby granted a copyright license to use, modify, and distribute the SOFTWARE
24 so long as this entire notice is retained without alteration in any modified and/or
25 redistributed versions, and that such modified versions are clearly identified as such.
31 # and contains the entry points into the package. The user, in
39 # it makes the ISP code easier to read and more mainatinable.
98 mov.l %d0,-(%sp)
99 mov.l (_060ISP_TABLE-0x80+_off_chk,%pc),%d0
100 pea.l (_060ISP_TABLE-0x80,%pc,%d0)
106 mov.l %d0,-(%sp)
107 mov.l (_060ISP_TABLE-0x80+_off_divbyzero,%pc),%d0
108 pea.l (_060ISP_TABLE-0x80,%pc,%d0)
114 mov.l %d0,-(%sp)
115 mov.l (_060ISP_TABLE-0x80+_off_trace,%pc),%d0
116 pea.l (_060ISP_TABLE-0x80,%pc,%d0)
122 mov.l %d0,-(%sp)
123 mov.l (_060ISP_TABLE-0x80+_off_access,%pc),%d0
124 pea.l (_060ISP_TABLE-0x80,%pc,%d0)
130 mov.l %d0,-(%sp)
131 mov.l (_060ISP_TABLE-0x80+_off_done,%pc),%d0
132 pea.l (_060ISP_TABLE-0x80,%pc,%d0)
140 mov.l %d0,-(%sp)
141 mov.l (_060ISP_TABLE-0x80+_off_cas,%pc),%d0
142 pea.l (_060ISP_TABLE-0x80,%pc,%d0)
148 mov.l %d0,-(%sp)
149 mov.l (_060ISP_TABLE-0x80+_off_cas2,%pc),%d0
150 pea.l (_060ISP_TABLE-0x80,%pc,%d0)
156 mov.l %d0,-(%sp)
157 mov.l (_060ISP_TABLE-0x80+_off_lock,%pc),%d0
158 pea.l (_060ISP_TABLE-0x80,%pc,%d0)
164 mov.l %d0,-(%sp)
165 mov.l (_060ISP_TABLE-0x80+_off_unlock,%pc),%d0
166 pea.l (_060ISP_TABLE-0x80,%pc,%d0)
174 mov.l %d0,-(%sp)
175 mov.l (_060ISP_TABLE-0x80+_off_imr,%pc),%d0
176 pea.l (_060ISP_TABLE-0x80,%pc,%d0)
182 mov.l %d0,-(%sp)
183 mov.l (_060ISP_TABLE-0x80+_off_dmr,%pc),%d0
184 pea.l (_060ISP_TABLE-0x80,%pc,%d0)
190 mov.l %d0,-(%sp)
191 mov.l (_060ISP_TABLE-0x80+_off_dmw,%pc),%d0
192 pea.l (_060ISP_TABLE-0x80,%pc,%d0)
198 mov.l %d0,-(%sp)
199 mov.l (_060ISP_TABLE-0x80+_off_irw,%pc),%d0
200 pea.l (_060ISP_TABLE-0x80,%pc,%d0)
206 mov.l %d0,-(%sp)
207 mov.l (_060ISP_TABLE-0x80+_off_irl,%pc),%d0
208 pea.l (_060ISP_TABLE-0x80,%pc,%d0)
214 mov.l %d0,-(%sp)
215 mov.l (_060ISP_TABLE-0x80+_off_drb,%pc),%d0
216 pea.l (_060ISP_TABLE-0x80,%pc,%d0)
222 mov.l %d0,-(%sp)
223 mov.l (_060ISP_TABLE-0x80+_off_drw,%pc),%d0
224 pea.l (_060ISP_TABLE-0x80,%pc,%d0)
230 mov.l %d0,-(%sp)
231 mov.l (_060ISP_TABLE-0x80+_off_drl,%pc),%d0
232 pea.l (_060ISP_TABLE-0x80,%pc,%d0)
238 mov.l %d0,-(%sp)
239 mov.l (_060ISP_TABLE-0x80+_off_dwb,%pc),%d0
240 pea.l (_060ISP_TABLE-0x80,%pc,%d0)
246 mov.l %d0,-(%sp)
247 mov.l (_060ISP_TABLE-0x80+_off_dww,%pc),%d0
248 pea.l (_060ISP_TABLE-0x80,%pc,%d0)
254 mov.l %d0,-(%sp)
255 mov.l (_060ISP_TABLE-0x80+_off_dwl,%pc),%d0
256 pea.l (_060ISP_TABLE-0x80,%pc,%d0)
266 set LV, -LOCAL_SIZE # stack offset
308 set mda7_flg, 0x08 # -(a7) flag
311 set restore_flg, 0x40 # restore -(an)+ flag
315 set mda7_bit, 0x3 # -(a7) bit
318 set restore_bit, 0x6 # restore -(a7)+ bit
337 # _imem_read_{word,long}() - read instruction word/longword #
338 # _mul64() - emulate 64-bit multiply #
339 # _div64() - emulate 64-bit divide #
340 # _moveperipheral() - emulate "movep" #
341 # _compandset() - emulate misaligned "cas" #
342 # _compandset2() - emulate "cas2" #
343 # _chk2_cmp2() - emulate "cmp2" and "chk2" #
344 # _isp_done() - "callout" for normal final exit #
345 # _real_trace() - "callout" for Trace exception #
346 # _real_chk() - "callout" for Chk exception #
347 # _real_divbyzero() - "callout" for DZ exception #
348 # _real_access() - "callout" for access error exception #
351 # - The system stack contains the Unimp Int Instr stack frame #
355 # - The system stack changed to contain Trace exc stack frame #
357 # - The system stack changed to contain Chk exc stack frame #
359 # - The system stack changed to contain DZ exc stack frame #
361 # - The system stack changed to contain access err exc stk frame #
363 # - Results saved as appropriate #
367 # memory and decodes it to determine which of the unimplemented #
372 # types of exceptions. "div" can produce a divide-by-zero exception, #
373 # and "chk2" can cause a "Chk" exception. In both cases, the current #
375 # of the correct exception type and an exit must be made through #
378 # a Trace exception stack frame must be created and an exit made #
382 # access error frame must be created and an exit made through #
387 # This handler, upon entry, saves almost all user-visible #
388 # address and data registers to the stack. Although this may seem to #
390 # access these register files for things like data retrieval and <ea> #
399 link.w %a6,&-LOCAL_SIZE # create room for stack frame
401 movm.l &0x3fff,EXC_DREGS(%a6) # store d0-d7/a0-a5
423 # fetch the opword and first extension word pointed to by the stacked pc
424 # and store them to the stack for now
478 # mul64() may use ()+ addressing and may, therefore, alter a7
491 # div64() may use ()+ addressing and may, therefore, alter a7.
500 btst &idbyz_bit,SPCOND_FLG(%a6) # did divide-by-zero occur?
510 # (iii) (a7)+; divide-by-zero
512 btst &idbyz_bit,SPCOND_FLG(%a6) # did divide-by-zero occur?
534 swap %d0 # put opword in lo word
542 # the cases of "cas Dc,Du,(a7)+" and "cas Dc,Du,-(a7)" used from supervisor
543 # mode are simply not considered valid and therefore are not handled.
573 # info and prepare for rte
588 movm.l EXC_DREGS(%a6),&0x3fff # restore d0-d7/a0-a5
603 # format number zero and jump to the user supplied hook "_real_trace()".
614 # ->* Old * *****************
615 # from link -->* A6 * * SR *
617 # /* A7 * * New * <-- for final unlink
624 mov.l EXC_A6(%a6),-0x4(%a6)
650 # and jump to the user supplied entry point "_real_chk()".
654 movm.l EXC_DREGS(%a6),&0x3fff # restore d0-d7/a0-a5
683 # instruction exception frame and jump to the user supplied entry point
688 movm.l EXC_DREGS(%a6),&0x3fff # restore d0-d7/a0-a5
717 # instruction exception frame and jump to the user supplied entry point
725 movm.l EXC_DREGS(%a6),&0x3fff # restore d0-d7/a0-a5
756 # format number zero and jump to the user supplied hook "_real_trace()".
763 movm.l EXC_DREGS(%a6),&0x3fff # restore d0-d7/a0-a5
790 movm.l EXC_DREGS(%a6),&0x3fff # restore d0-d7/a0-a5
807 mov.l %d0,-0x4(%a6) # save partial fslw
809 lea -64(%a6),%sp
810 movm.l (%sp)+,&0x7fff # restore d0-d7/a0-a6
812 mov.l 0xc(%sp),-(%sp) # move voff,hi(pc)
829 movm.l EXC_DREGS(%a6),&0x3fff # restore d0-d7/a0-a5
845 # if the addressing mode was (an)+ or -(an), the address register must
846 # be restored to its pre-exception value before entering _real_access.
861 # _imem_read_word() - read instruction word #
862 # _imem_read_long() - read instruction longword #
863 # _dmem_read_long() - read data longword (for memory indirect) #
864 # isp_iacc() - handle instruction access error exception #
865 # isp_dacc() - handle data access error exception #
883 # uses byte-sized operands, only handle word and long operations. #
885 # Dn,An - shouldn't enter here #
886 # (An) - fetch An value from stack #
887 # -(An) - fetch An value from stack; return decr value; #
889 # future access error; if -(a7), set mda7_flg in #
891 # (An)+ - fetch An value from stack; return value; #
895 # (d16,An) - fetch An value from stack; read d16 using #
896 # _imem_read_word(); fetch may fail -> branch to #
898 # (xxx).w,(xxx).l - use _imem_read_{word,long}() to fetch #
900 # #<data> - return address of immediate value; set immed_flg #
902 # (d16,PC) - fetch stacked PC value; read d16 using #
903 # _imem_read_word(); fetch may fail -> branch to #
905 # everything else - read needed displacements as appropriate w/ #
916 # MODE and REG are taken from the EXC_OPWORD.
929 short tbl_ea_mode - tbl_ea_mode
930 short tbl_ea_mode - tbl_ea_mode
931 short tbl_ea_mode - tbl_ea_mode
932 short tbl_ea_mode - tbl_ea_mode
933 short tbl_ea_mode - tbl_ea_mode
934 short tbl_ea_mode - tbl_ea_mode
935 short tbl_ea_mode - tbl_ea_mode
936 short tbl_ea_mode - tbl_ea_mode
938 short tbl_ea_mode - tbl_ea_mode
939 short tbl_ea_mode - tbl_ea_mode
940 short tbl_ea_mode - tbl_ea_mode
941 short tbl_ea_mode - tbl_ea_mode
942 short tbl_ea_mode - tbl_ea_mode
943 short tbl_ea_mode - tbl_ea_mode
944 short tbl_ea_mode - tbl_ea_mode
945 short tbl_ea_mode - tbl_ea_mode
947 short addr_ind_a0 - tbl_ea_mode
948 short addr_ind_a1 - tbl_ea_mode
949 short addr_ind_a2 - tbl_ea_mode
950 short addr_ind_a3 - tbl_ea_mode
951 short addr_ind_a4 - tbl_ea_mode
952 short addr_ind_a5 - tbl_ea_mode
953 short addr_ind_a6 - tbl_ea_mode
954 short addr_ind_a7 - tbl_ea_mode
956 short addr_ind_p_a0 - tbl_ea_mode
957 short addr_ind_p_a1 - tbl_ea_mode
958 short addr_ind_p_a2 - tbl_ea_mode
959 short addr_ind_p_a3 - tbl_ea_mode
960 short addr_ind_p_a4 - tbl_ea_mode
961 short addr_ind_p_a5 - tbl_ea_mode
962 short addr_ind_p_a6 - tbl_ea_mode
963 short addr_ind_p_a7 - tbl_ea_mode
965 short addr_ind_m_a0 - tbl_ea_mode
966 short addr_ind_m_a1 - tbl_ea_mode
967 short addr_ind_m_a2 - tbl_ea_mode
968 short addr_ind_m_a3 - tbl_ea_mode
969 short addr_ind_m_a4 - tbl_ea_mode
970 short addr_ind_m_a5 - tbl_ea_mode
971 short addr_ind_m_a6 - tbl_ea_mode
972 short addr_ind_m_a7 - tbl_ea_mode
974 short addr_ind_disp_a0 - tbl_ea_mode
975 short addr_ind_disp_a1 - tbl_ea_mode
976 short addr_ind_disp_a2 - tbl_ea_mode
977 short addr_ind_disp_a3 - tbl_ea_mode
978 short addr_ind_disp_a4 - tbl_ea_mode
979 short addr_ind_disp_a5 - tbl_ea_mode
980 short addr_ind_disp_a6 - tbl_ea_mode
981 short addr_ind_disp_a7 - tbl_ea_mode
983 short _addr_ind_ext - tbl_ea_mode
984 short _addr_ind_ext - tbl_ea_mode
985 short _addr_ind_ext - tbl_ea_mode
986 short _addr_ind_ext - tbl_ea_mode
987 short _addr_ind_ext - tbl_ea_mode
988 short _addr_ind_ext - tbl_ea_mode
989 short _addr_ind_ext - tbl_ea_mode
990 short _addr_ind_ext - tbl_ea_mode
992 short abs_short - tbl_ea_mode
993 short abs_long - tbl_ea_mode
994 short pc_ind - tbl_ea_mode
995 short pc_ind_ext - tbl_ea_mode
996 short immediate - tbl_ea_mode
997 short tbl_ea_mode - tbl_ea_mode
998 short tbl_ea_mode - tbl_ea_mode
999 short tbl_ea_mode - tbl_ea_mode
1126 # Address register indirect w/ predecrement: -(An) #
1314 # Address register indirect w/ index(8-bit displacement): (dn, An, Xn) #
1320 mov.l %d1,-(%sp)
1336 movm.l &0x3c00,-(%sp) # save d2-d5
1344 mov.l %d2,-(%sp) # save old d2
1431 # PC indirect w/ index(8-bit displacement): (d8, PC, An) #
1452 movm.l &0x3c00,-(%sp) # save d2-d5
1460 mov.l %d2,-(%sp) # create a temp register
1600 movm.l (%sp)+,&0x003c # restore d2-d5
1605 # and the failing address to the routine that creates the new frame.
1621 # _dmem_read_byte() - read byte from memory #
1622 # _dmem_write_byte() - write byte to memory #
1623 # isp_dacc() - handle data access error exception #
1636 # Decode the movep instruction words stored at EXC_OPWORD and #
1639 # returns a failing value, we must pass the failing address and a FSLW #
1655 and.w &0x7,%d0 # extract Ay from opcode word
1668 and.w &0x7,%d0 # extract Dx from opcode word
1744 # determines the dest register, and then writes the bytes into it.
1795 and.w &0x7,%d1 # extract Dx from opcode word
1825 and.w &0x7,%d1 # extract Dx from opcode word
1833 # and the failing address to the routine that creates the new frame.
1882 # The comparisons are made and the condition codes calculated. #
1883 # If the instruction is chk2 and the Rn value is out-of-bounds, set #
1886 # address and FSLW to the isp_dacc() routine. #
1899 and.w &0xf, %d0 # extract reg bits
1908 # bound into d0 and the higher bound into d1.
1926 bra.w chk2_cmp2_compare # go do the compare emulation
1939 swap %d0 # place lo in %d0
1944 btst &0x7, EXC_EXTWORD(%a6) # address compare?
1947 # operation is a data register compare.
1950 bra.w chk2_cmp2_compare # go emulate compare
1968 btst &0x7, EXC_EXTWORD(%a6) # address compare?
1971 # operation is a data register compare.
1977 # (1) save 'Z' bit from (Rn - lo)
1978 # (2) save 'Z' and 'N' bits from ((hi - lo) - (Rn - hi))
1979 # (3) keep 'X', 'N', and 'V' from before instruction
1983 sub.l %d0, %d2 # (Rn - lo)
1986 sub.l %d0, %d1 # (hi - lo)
1987 cmp.l %d1,%d2 # ((hi - lo) - (Rn - hi))
1991 andi.b &0x5, %d3 # keep 'Z' and 'N'
2003 # this code handles the only difference between chk2 and cmp2. chk2 would
2016 # and the failing address to the routine that creates the new frame.
2040 # 64/32->32r:32q #
2043 # _calc_ea() - calculate effective address #
2044 # isp_iacc() - handle instruction access error exception #
2045 # isp_dacc() - handle data access error exception #
2046 # isp_restore() - restore An on access error w/ -() or ()+ #
2064 # If the operands are signed, make them unsigned and save the #
2065 # sign info for later. Separate out special cases like divide-by-zero #
2066 # or 32-bit divides if possible. Else, use a special math algorithm #
2070 # quotient and remainder in the appropriate data registers on the stack.#
2101 and.w &0x7, %d0
2103 and.w &0x7, %d1
2107 # fetch %dr and %dq directly off stack since all regs are saved there
2111 # separate signed and unsigned divide
2134 # - is (dividend == 0) ?
2135 # - is (hi(dividend) == 0 && (divisor <= lo(dividend))) ? (32-bit div)
2156 # - is hi(dividend) >= divisor ? if yes, then overflow
2163 # separate into signed and unsigned finishes.
2177 # 0x80000000 is the largest number representable as a 32-bit negative
2179 cmpi.l %d6, &0x80000000 # will (-quot) fit in 32 bits?
2182 neg.l %d6 # make (-quot) 2's comp
2221 # For this implementation b=2**16, and the target is U1U2U3U4/V1V2, #
2222 # where U,V are words of the quadword dividend and longword divisor, #
2223 # and U1, V1 are the most significant words. #
2226 # in %d6. The divisor must be in the variable ddivisor, and the #
2239 # Since the divisor is only a word (and larger than the mslw of the dividend),
2245 # longword of the dividend as (0) remainder (see Knuth) and merely complete
2246 # the last two divisions to get a quotient longword and word remainder:
2249 swap %d5 # same as r*b if previous step rqd
2250 swap %d6 # get u3 to lsw position
2256 swap %d6 # get u4
2261 swap %d1
2264 swap %d5 # now remainder
2265 mov.l %d1, %d6 # and quotient
2272 # digit (word). After subtraction, the dividend is shifted and the
2273 # process repeated. Before beginning, the divisor and quotient are
2294 swap %d2
2295 swap %d3
2308 # now test the trial quotient and adjust. This step plus the
2311 mov.l %d6, -(%sp)
2313 swap %d6 # in lsw position
2317 swap %d3
2320 sub.l %d3, %d4 # U1U2 - V1q
2322 swap %d4
2330 # add.l %d6, %d4 # (U1U2 - V1q) + U3
2333 bls.b ddadjd1 # is V2q > (U1U2-V1q) + U3 ?
2334 subq.l &0x1, %d1 # yes, decrement and recheck
2337 # now test the word by multiplying it by the divisor (V1V2) and comparing
2339 mov.l %d5, -(%sp) # save %d5 (%d6 already saved)
2341 swap %d6 # shift answer to ms 3 words
2353 # - according to Knuth, this is done only 2 out of 65536 times for random
2357 swap %d3
2363 swap %d3 # aligned with 2nd word of dividend
2368 # first quotient digit now correct. store digit and shift the
2372 swap %d5
2373 swap %d6
2383 swap %d6
2384 swap %d5
2398 # factors for the 32X32->64 multiplication are in %d5 and %d6.
2406 swap %d3
2407 swap %d4
2408 mulu.w %d5, %d6 # %d6 <- lsw*lsw
2409 mulu.w %d3, %d5 # %d5 <- msw-dest*lsw-source
2410 mulu.w %d4, %d2 # %d2 <- msw-source*lsw-dest
2411 mulu.w %d4, %d3 # %d3 <- msw*msw
2412 # now use swap and addx to consolidate to two longwords
2414 swap %d6
2419 swap %d6 # %d6 is low 32 bits of final product
2422 swap %d5 # now use msws of longwords
2423 swap %d2
2462 # and the failing address to the routine that creates the new frame.
2464 # (an)+ or -(an) in which case the previous "an" value must be restored.
2478 # _mul64(): routine to emulate mul{u,s}.l <ea>,Dh:Dl 32x32->64 #
2481 # _calc_ea() - calculate effective address #
2482 # isp_iacc() - handle instruction access error exception #
2483 # isp_dacc() - handle data access error exception #
2484 # isp_restore() - restore An on access error w/ -() or ()+ #
2502 # If the operands are signed, make them unsigned and save the #
2503 # sign info for later. Perform the multiplication using 16x16->32 #
2504 # unsigned multiplies and "add" instructions. Store the high and low #
2520 # must extract the register number and fetch the operand from the stack.
2525 # multiplier is in %d3. now, extract Dl and Dh fields and fetch the
2542 # multiplier is in %d3 and multiplicand is in %d4.
2544 # to unsigned and the result sign is saved for the end.
2563 # ---------------------------- #
2565 # ---------------------------- #
2566 # ----------------------------- #
2568 # ----------------------------- #
2569 # ----------------------------- #
2571 # ----------------------------- #
2572 # | ----------------------------- #
2573 # --|-- | lo(mplier) * lo(mplicand) | #
2574 # | ----------------------------- #
2576 # -------------------------------------------------------- #
2578 # -------------------------------------------------------- #
2585 swap %d6 # hi(mr) in lo %d6
2586 swap %d7 # hi(md) in lo %d7
2598 swap %d3 # hi([1]) <==> lo([1])
2603 swap %d3 # lo([1]) <==> hi([1])
2606 # now, clear lo, put hi in lo reg, and add to [4]
2609 swap %d4 # hi([2]) in lo %d4
2610 swap %d5 # hi([3]) in lo %d5
2620 # -negate all bits and add 1
2645 or.b %d7, %d6 # group 'X' and 'N'
2651 # save the zero result to the register file and set the 'Z' ccode bit.
2662 # must calculate the <ea> and go fetch the 32-bit operand.
2697 # and the failing address to the routine that creates the new frame.
2699 # (an)+ or -(an) in which case the previous "an" value must be restored.
2716 # _isp_cas2_finish(): store ccodes, store compare regs #
2720 # _real_lock_page() - "callout" to lock op's page from page-outs #
2721 # _cas_terminate2() - access error exit #
2722 # _real_cas2() - "callout" to core cas2 emulation code #
2723 # _real_unlock_page() - "callout" to unlock page #
2741 # Decode the instruction and fetch the appropriate Update and #
2742 # Compare operands. Then call the "callout" _real_lock_page() for each #
2746 # using _real_unlock_paged() if the 2nd lock-page fails. #
2751 # Re-perform the comparison so we can determine the condition #
2833 mov.l %d0,-(%sp) # save FSLW
2856 tst.b %d4 # update compare reg?
2887 tst.b %d4 # update compare reg?
2921 # (external and internal to package) #
2925 # (external and internal to package) #
2957 # d0 = 0 => in range; -1 => out of range #
2963 # instruction word and fetch the "compare" (DC) and "update" (Du) #
2974 # Either way, after emulation, the package is re-entered at #
2975 # _isp_cas_finish(). This routine re-compares the operands in order to #
2982 # the emulation sequence should be re-started from the beginning. #
2986 # an emulation operand access failed and the operating system would #
3030 mov.l (EXC_DREGS,%a6,%d1.w*4),%d4 # get compare operand
3052 # just do the compare again since it's faster than saving the ccodes
3056 cmp.w %d0,%d4 # do word compare
3059 tst.b %d1 # update compare reg?
3073 # just do the compare again since it's faster than saving the ccodes
3077 cmp.l %d0,%d4 # do longword compare
3080 tst.b %d1 # update compare reg?
3121 mov.l %d0,-(%sp)
3122 bsr.l isp_restore # restore An (if ()+ or -())
3155 mov.l &-0x1,%d0 # out of range; return d0 = -1
3161 # This is the start of the cas and cas2 "core" emulation code. #
3163 # OS if it is too operating system-specific. #
3181 # _isp_cas2_finish() - only exit point for this emulation code; #
3182 # do clean-up; calculate ccodes; store #
3183 # Compare Ops if appropriate. #
3197 # (4) Use "plpaw" instruction to pre-load ATC with effective #
3204 # (6) Use "plpar" instruction to do a re-load of ATC entries for #
3207 # (7) Pre-fetch the core emulation instructions by executing #
3215 # the bus (and assert LOCKE*) using BUSCR and the final move. #
3222 # depending on the size of the operation and the misalignment of the #
3279 # mask interrupts levels 0-6. save old mask value.
3283 # load the SFC and DFC with the appropriate mode.
3288 # pre-load the operand ATC. no page faults should occur here because
3304 # if ADDR1 was ATC resident before the above "plpaw" and was executed
3305 # and it was the next entry scheduled for replacement and ADDR2
3316 # there are three possible mis-aligned cases for longword cas. they
3327 # D0 = dst operand 1 <-
3328 # D1 = dst operand 2 <-
3352 cmp.l %d0,%d2 # Dest1 - Compare1
3354 cmp.l %d1,%d3 # Dest2 - Compare2
3356 movs.l %d5,(%a1) # Update2[31:0] -> DEST2
3362 movs.l %d4,(%a0) # Update1[31:0] -> DEST1
3369 movs.l %d0,(%a0) # Dest1[31:0] -> DEST1
3394 # D4 = 'xxxxxx11 -> no reg update; 'xxxxxx00 -> update required #
3443 cmp.l %d0,%d2 # Dest1 - Compare1
3445 cmp.l %d1,%d3 # Dest2 - Compare2
3447 movs.l %d5,(%a1) # Update2[31:0] -> Dest2
3452 swap %d4 # get Update1[31:16]
3453 movs.w %d4,(%a0)+ # Update1[31:16] -> DEST1
3455 swap %d4 # get Update1[15:0]
3460 movs.w %d4,(%a0) # Update1[15:0] -> DEST1+0x2
3467 swap %d0 # get Dest1[31:16]
3468 movs.w %d0,(%a0)+ # Dest1[31:16] -> DEST1
3470 swap %d0 # get Dest1[15:0]
3475 movs.w %d0,(%a0) # Dest1[15:0] -> DEST1+0x2
3503 cmp.l %d0,%d2 # Dest1 - Compare1
3505 cmp.l %d1,%d3 # Dest2 - Compare2
3507 movs.l %d5,(%a1) # Update2[31:0] -> DEST2
3513 movs.b %d4,(%a0)+ # Update1[31:24] -> DEST1
3514 swap %d4 # get Update1[23:8]
3515 movs.w %d4,(%a0)+ # Update1[23:8] -> DEST1+0x1
3522 movs.b %d4,(%a0) # Update1[7:0] -> DEST1+0x3
3537 movs.b %d0,(%a0)+ # Dest1[31:24] -> DEST1
3538 swap %d0 # get Dest1[23:8]
3539 movs.w %d0,(%a0)+ # Dest1[23:8] -> DEST1+0x1
3546 movs.b %d0,(%a0) # Update1[7:0] -> DEST1+0x3
3581 # mask interrupt levels 0-6. save old mask value.
3585 # load the SFC and DFC with the appropriate mode.
3590 # pre-load the operand ATC. no page faults should occur because
3606 # if ADDR1 was ATC resident before the above "plpaw" and was executed
3607 # and it was the next entry scheduled for replacement and ADDR2
3618 # there are two possible mis-aligned cases for word cas. they
3627 # D0 = dst operand 1 <-
3628 # D1 = dst operand 2 <-
3652 cmp.w %d0,%d2 # Dest1 - Compare1
3654 cmp.w %d1,%d3 # Dest2 - Compare2
3656 movs.w %d5,(%a1) # Update2[15:0] -> DEST2
3662 movs.w %d4,(%a0) # Update1[15:0] -> DEST1
3669 movs.w %d0,(%a0) # Dest1[15:0] -> DEST1
3694 # D4 = 'xxxxxx11 -> no reg update; 'xxxxxx00 -> update required #
3743 cmp.w %d0,%d2 # Dest1 - Compare1
3745 cmp.w %d1,%d3 # Dest2 - Compare2
3747 movs.w %d5,(%a1) # Update2[15:0] -> DEST2
3753 movs.b %d4,(%a0)+ # Update1[15:8] -> DEST1
3760 movs.b %d4,(%a0) # Update1[7:0] -> DEST1+0x1
3768 movs.b %d0,(%a0)+ # Dest1[15:8] -> DEST1
3775 movs.b %d0,(%a0) # Dest1[7:0] -> DEST1+0x1
3802 # _isp_cas_finish() - only exit point for this emulation code; #
3803 # do clean-up #
3817 # (4) Use "plpaw" instruction to pre-load ATC with effective #
3824 # (6) Pre-fetch the core emulation instructions by executing one #
3829 # (9) Do the compare. If equal, go to step (12). #
3832 # the bus (and assert LOCKE*) using BUSCR and the final move. #
3839 # depending on the size of the operation and the misalignment of the #
3853 # D4 = compare operand #
3890 # mask interrupt levels 0-6. save old mask value.
3894 # load the SFC and DFC with the appropriate mode.
3899 # pre-load the operand ATC. no page faults should occur here because
3913 # pre-load the instruction cache for the following algorithm.
3915 bra.b CASW_ENTER # start pre-loading icache
3918 # D0 = dst operand <-
3922 # D4 = compare[15:0] operand
3937 cmp.w %d0,%d4 # Dest - Compare
3944 movs.b %d2,(%a0)+ # Update[15:8] -> DEST
3946 movs.b %d3,(%a0) # Update[7:0] -> DEST+0x1
3961 movs.b %d0,(%a0)+ # Dest[15:8] -> DEST
3968 movs.b %d0,(%a0) # Dest[7:0] -> DEST+0x1
3990 # D1 = 'xxxxxx11 -> no reg update; 'xxxxxx00 -> update required #
3993 # D4 = compare[15:0] operand #
4033 # there are two possible mis-aligned cases for longword cas. they
4046 swap %d2 # d2 = update[31:16]
4048 # mask interrupts levels 0-6. save old mask value.
4052 # load the SFC and DFC with the appropriate mode.
4057 # pre-load the operand ATC. no page faults should occur here because
4071 bra.b CASL_ENTER # start pre-loading icache
4074 # D0 = dst operand <-
4078 # D4 = compare[31:0] operand
4093 cmp.l %d0,%d4 # Dest - Compare
4100 movs.w %d2,(%a0)+ # Update[31:16] -> DEST
4102 movs.w %d3,(%a0) # Update[15:0] -> DEST+0x2
4116 swap %d0 # get Dest[31:16]
4117 movs.w %d0,(%a0)+ # Dest[31:16] -> DEST
4118 swap %d0 # get Dest[15:0]
4124 movs.w %d0,(%a0) # Dest[15:0] -> DEST+0x2
4146 # D1 = 'xxxxxx11 -> no reg update; 'xxxxxx00 -> update required #
4149 # D4 = compare[31:0] operand #
4192 swap %d2 # d2 = Update[31:24]
4194 # mask interrupts levels 0-6. save old mask value.
4198 # load the SFC and DFC with the appropriate mode.
4203 # pre-load the operand ATC. no page faults should occur here because
4217 # pre-load the instruction cache for the following algorithm.
4219 bra.b CASL2_ENTER # start pre-loading icache
4222 # D0 = dst operand <-
4226 # D4 = compare[31:0] operand
4241 cmp.l %d0,%d4 # Dest - Compare
4248 movs.b %d2,(%a0)+ # Update[31:24] -> DEST
4249 movs.w %d3,(%a0)+ # Update[23:8] -> DEST+0x1
4255 movs.b %d5,(%a0) # Update[7:0] -> DEST+0x3
4263 movs.b %d0,(%a0)+ # Dest[31:24] -> DEST
4264 swap %d0 # get Dest[23:8]
4265 movs.w %d0,(%a0)+ # Dest[23:8] -> DEST+0x1
4272 movs.b %d0,(%a0) # Dest[7:0] -> DEST+0x3