4  * Copyright (C) 2007-2009 Michal Simek <[email protected]>
5  * Copyright (C) 2007-2009 PetaLogix
6  * Copyright (C) 2007-2009 John Williams <[email protected]>
89  * End address can be unaligned which is OK for C implementation.
90  * ASM implementation align it in ASM macros
92 #define CACHE_LOOP_LIMITS(start, end, cache_line_length, cache_size)	\  argument
94 	int align = ~(cache_line_length - 1);				\
95 	if (start <  UINT_MAX - cache_size)				\
96 		end = min(start + cache_size, end);			\
97 	start &= align;							\
106 	unsigned int len = cache_size - line_length;			\
107 	int step = -line_length;					\
121  * end address is not aligned, if end is aligned then I have to subtract
123  * If is not, I align it because I will flush/invalidate whole line.
125 #define CACHE_RANGE_LOOP_2(start, end, line_length, op)			\  argument
127 	int step = -line_length;					\
128 	int align = ~(line_length - 1);					\
130 	end = ((end & align) == end) ? end - line_length : end & align;	\
131 	count = end - start;						\
141 /* It is used only first parameter for OP - for wic, wdc */
142 #define CACHE_RANGE_LOOP_1(start, end, line_length, op)			\  argument
145 	unsigned int align = ~(line_length - 1);					\
146 	end = ((end & align) == end) ? end - line_length : end & align;	\
147 	WARN_ON(end < start);					\
153 				: : "r" (temp), "r" (start), "r" (end),	\
159 static void __flush_icache_range_msr_irq(unsigned long start, unsigned long end)  in __flush_icache_range_msr_irq()  argument
165 	pr_debug("%s: start 0x%x, end 0x%x\n", __func__,  in __flush_icache_range_msr_irq()
166 				(unsigned int)start, (unsigned int) end);  in __flush_icache_range_msr_irq()
168 	CACHE_LOOP_LIMITS(start, end,  in __flush_icache_range_msr_irq()
175 	CACHE_RANGE_LOOP_1(start, end, cpuinfo.icache_line_length, wic);  in __flush_icache_range_msr_irq()
177 	for (i = start; i < end; i += cpuinfo.icache_line_length)  in __flush_icache_range_msr_irq()
186 				unsigned long end)  in __flush_icache_range_nomsr_irq()  argument
192 	pr_debug("%s: start 0x%x, end 0x%x\n", __func__,  in __flush_icache_range_nomsr_irq()
193 				(unsigned int)start, (unsigned int) end);  in __flush_icache_range_nomsr_irq()
195 	CACHE_LOOP_LIMITS(start, end,  in __flush_icache_range_nomsr_irq()
202 	CACHE_RANGE_LOOP_1(start, end, cpuinfo.icache_line_length, wic);  in __flush_icache_range_nomsr_irq()
204 	for (i = start; i < end; i += cpuinfo.icache_line_length)  in __flush_icache_range_nomsr_irq()
214 				unsigned long end)  in __flush_icache_range_noirq()  argument
219 	pr_debug("%s: start 0x%x, end 0x%x\n", __func__,  in __flush_icache_range_noirq()
220 				(unsigned int)start, (unsigned int) end);  in __flush_icache_range_noirq()
222 	CACHE_LOOP_LIMITS(start, end,  in __flush_icache_range_noirq()
225 	CACHE_RANGE_LOOP_1(start, end, cpuinfo.icache_line_length, wic);  in __flush_icache_range_noirq()
227 	for (i = start; i < end; i += cpuinfo.icache_line_length)  in __flush_icache_range_noirq()
378 						unsigned long end)  in __invalidate_dcache_range_wb()  argument
383 	pr_debug("%s: start 0x%x, end 0x%x\n", __func__,  in __invalidate_dcache_range_wb()
384 				(unsigned int)start, (unsigned int) end);  in __invalidate_dcache_range_wb()
386 	CACHE_LOOP_LIMITS(start, end,  in __invalidate_dcache_range_wb()
389 	CACHE_RANGE_LOOP_2(start, end, cpuinfo.dcache_line_length, wdc.clear);  in __invalidate_dcache_range_wb()
391 	for (i = start; i < end; i += cpuinfo.dcache_line_length)  in __invalidate_dcache_range_wb()
398 							unsigned long end)  in __invalidate_dcache_range_nomsr_wt()  argument
403 	pr_debug("%s: start 0x%x, end 0x%x\n", __func__,  in __invalidate_dcache_range_nomsr_wt()
404 				(unsigned int)start, (unsigned int) end);  in __invalidate_dcache_range_nomsr_wt()
405 	CACHE_LOOP_LIMITS(start, end,  in __invalidate_dcache_range_nomsr_wt()
409 	CACHE_RANGE_LOOP_1(start, end, cpuinfo.dcache_line_length, wdc);  in __invalidate_dcache_range_nomsr_wt()
411 	for (i = start; i < end; i += cpuinfo.dcache_line_length)  in __invalidate_dcache_range_nomsr_wt()
418 							unsigned long end)  in __invalidate_dcache_range_msr_irq_wt()  argument
424 	pr_debug("%s: start 0x%x, end 0x%x\n", __func__,  in __invalidate_dcache_range_msr_irq_wt()
425 				(unsigned int)start, (unsigned int) end);  in __invalidate_dcache_range_msr_irq_wt()
426 	CACHE_LOOP_LIMITS(start, end,  in __invalidate_dcache_range_msr_irq_wt()
433 	CACHE_RANGE_LOOP_1(start, end, cpuinfo.dcache_line_length, wdc);  in __invalidate_dcache_range_msr_irq_wt()
435 	for (i = start; i < end; i += cpuinfo.dcache_line_length)  in __invalidate_dcache_range_msr_irq_wt()
445 							unsigned long end)  in __invalidate_dcache_range_nomsr_irq()  argument
451 	pr_debug("%s: start 0x%x, end 0x%x\n", __func__,  in __invalidate_dcache_range_nomsr_irq()
452 				(unsigned int)start, (unsigned int) end);  in __invalidate_dcache_range_nomsr_irq()
454 	CACHE_LOOP_LIMITS(start, end,  in __invalidate_dcache_range_nomsr_irq()
461 	CACHE_RANGE_LOOP_1(start, end, cpuinfo.dcache_line_length, wdc);  in __invalidate_dcache_range_nomsr_irq()
463 	for (i = start; i < end; i += cpuinfo.dcache_line_length)  in __invalidate_dcache_range_nomsr_irq()
489 static void __flush_dcache_range_wb(unsigned long start, unsigned long end)  in __flush_dcache_range_wb()  argument
494 	pr_debug("%s: start 0x%x, end 0x%x\n", __func__,  in __flush_dcache_range_wb()
495 				(unsigned int)start, (unsigned int) end);  in __flush_dcache_range_wb()
497 	CACHE_LOOP_LIMITS(start, end,  in __flush_dcache_range_wb()
500 	CACHE_RANGE_LOOP_2(start, end, cpuinfo.dcache_line_length, wdc.flush);  in __flush_dcache_range_wb()
502 	for (i = start; i < end; i += cpuinfo.dcache_line_length)  in __flush_dcache_range_wb()
605 /* CPU version code for 7.20.c - see arch/microblaze/kernel/cpu/cpuinfo.c */
616 				/* MS: problem with signal handling - hw bug */  in microblaze_cache_init()
633 				/* MS: problem with signal handling - hw bug */  in microblaze_cache_init()
647 	 * FIXME Invalidation is done in U-BOOT  in microblaze_cache_init()