Lines Matching full:t1
133 mfc0 t1,CP0_STATUS
138 and t0,t1 # isolate allowed ones
150 # open coded PTR_LA t1, cpu_mask_nr_tbl
152 # open coded la t1, cpu_mask_nr_tbl
153 lui t1, %hi(cpu_mask_nr_tbl)
154 addiu t1, %lo(cpu_mask_nr_tbl)
158 1: lw t2,(t1)
162 addu t1,2*PTRSIZE # delay slot
167 lw a0,(-PTRSIZE)(t1)
186 andi t1,t0,KN02_IRQ_ALL
196 lw t1,IO_REG_SIMR(t2) # get mask: IOASIC simr
199 1: and t0,t1 # mask out allowed ones
206 # open coded PTR_LA t1,asic_mask_nr_tbl
208 # open coded la t1, asic_mask_nr_tbl
209 lui t1, %hi(asic_mask_nr_tbl)
210 addiu t1, %lo(asic_mask_nr_tbl)
214 2: lw t2,(t1)
218 addu t1,2*PTRSIZE # delay slot
223 lw a0,%lo(-PTRSIZE)(t1)
239 li t1,CAUSEF_IP>>CAUSEB_IP # mask
245 li t1,KN02_IRQ_ALL # mask
251 li t1,IO_IRQ_ALL # mask
261 li t1,IO_IRQ_DMA>>IO_INR_DMA # mask
268 1: srlv t3,t1,t2
269 2: xor t1,t3
270 and t3,t0,t1
277 srlv t3,t1,t2
287 lw t1,(t0)
289 addu t1,1
291 sw t1,(t0)