Lines Matching +full:25 +full:- +full:18
19 #include <asm/isa-rev.h>
184 #define CP0_WATCHLO $18
185 #define C0_WATCHLO 18, 0
208 #define CP0_PERFORMANCE $25
209 #define C0_PERFORMANCE 25, 0
249 #define CP0_IWATCH $18
290 #define MIPS_ENTRYLO_XI (_ULCAST_(1) << (BITS_PER_LONG - 2))
291 #define MIPS_ENTRYLO_RI (_ULCAST_(1) << (BITS_PER_LONG - 1))
372 #define PL_256K 18
522 /* in-kernel enabled CUs */
600 #define EXCCODE_TLBRI 19 /* TLB Read-Inhibit exception */
601 #define EXCCODE_TLBXI 20 /* TLB Execution-Inhibit exception */
606 #define EXCCODE_THREAD 25 /* Thread exceptions (MT) */
615 #define LOONGSON_EXCCODE_GSEXC 16 /* Loongson-specific exception */
642 #define CONF_EW (_ULCAST_(3) << 18)
689 #define R30XX_CONF_HALT (_ULCAST_(1) << 25)
698 #define TX49_CONF_HALT (_ULCAST_(1) << 18)
717 #define MIPS_CONF_KU (_ULCAST_(3) << 25)
749 #define MIPS_CONF1_TLBS_SHIFT (25)
779 #define MIPS_CONF3_MMAR (_ULCAST_(7) << 18)
783 #define MIPS_CONF3_SC (_ULCAST_(1) << 25)
797 /* bits 10:8 in FTLB-only configurations */
799 /* bits 12:8 in VTLB-FTLB only configurations */
824 #define MIPS_CONF5_CRCP (_ULCAST_(1) << 18)
848 /* Config6 feature bits for Loongson-3 */
850 /* Loongson-3 internal timer bit */
852 /* Loongson-3 external timer bit */
854 /* Loongson-3 SFB on/off bit, STFill in manual */
856 /* Loongson-3's LL on exclusive cacheline */
858 /* Loongson-3's SC has a random delay */
860 /* Loongson-3 FTLB on/off bit, VTLBOnly in manual */
956 #define MIPS_EBASE_BASE (~_ULCAST_((1 << MIPS_EBASE_BASE_SHIFT) - 1))
960 #define MIPS_CMGCRF_BASE (~_ULCAST_((1 << MIPS_CMGCRB_BASE) - 1))
988 #define MIPS_PWFIELD_UDI_SHIFT 18
1001 #define MIPS_PWSIZE_UDW_SHIFT 18
1036 #define MIPS_GCTL0_GT_SHIFT 25
1046 #define MIPS_GCTL0_PT_SHIFT 18
1091 #define MIPS_GCTL0EXT_RPW_BOTH 0 /* Root PW for GPA->RPA and RVA->RPA */
1092 #define MIPS_GCTL0EXT_RPW_GPA 2 /* Root PW for GPA->RPA */
1093 #define MIPS_GCTL0EXT_RPW_RVA 3 /* Root PW for RVA->RPA */
1196 * Diag1 (GSCause in Loongson-speak) fields
1198 /* Loongson-specific exception code (GSExcCode) */
1228 #define CP1_FCCR $25
1239 #define MIPS_FPIR_PS (_ULCAST_(1) << 18)
1285 #define FPU_CSR_CONDX_S 25 /* $fcc[7:1] */
1287 #define FPU_CSR_COND1_S 25 /* $fcc1 */
1312 #define FPU_CSR_NAN2008 (_ULCAST_(1) << 18)
1346 #define FPU_CSR_RD 0x3 /* towards -Infinity */
1366 * microMIPS instructions can be 16-bit or 32-bit in length. This
1367 * returns a 1 if the instruction is 16-bit and a 0 if 32-bit.
1404 * parse_r var, r - Helper assembler macro for parsing register names.
1434 "\\var = -1\n\t" \
1439 _IFC_REG(16) _IFC_REG(17) _IFC_REG(18) _IFC_REG(19) \
1441 _IFC_REG(24) _IFC_REG(25) _IFC_REG(26) _IFC_REG(27) \
1524 * mfc0 and mtc0 instructions from and to coprocessor register with a 5-bit
1526 * Only performance counters 0 to 1 actually exist, so for a non-R10000 aware
1694 * physical address space running the 32-bit kernel. That's none atm :-)
1939 #define read_c0_watchlo0() __read_ulong_c0_register($18, 0)
1940 #define read_c0_watchlo1() __read_ulong_c0_register($18, 1)
1941 #define read_c0_watchlo2() __read_ulong_c0_register($18, 2)
1942 #define read_c0_watchlo3() __read_ulong_c0_register($18, 3)
1943 #define read_c0_watchlo4() __read_ulong_c0_register($18, 4)
1944 #define read_c0_watchlo5() __read_ulong_c0_register($18, 5)
1945 #define read_c0_watchlo6() __read_ulong_c0_register($18, 6)
1946 #define read_c0_watchlo7() __read_ulong_c0_register($18, 7)
1947 #define write_c0_watchlo0(val) __write_ulong_c0_register($18, 0, val)
1948 #define write_c0_watchlo1(val) __write_ulong_c0_register($18, 1, val)
1949 #define write_c0_watchlo2(val) __write_ulong_c0_register($18, 2, val)
1950 #define write_c0_watchlo3(val) __write_ulong_c0_register($18, 3, val)
1951 #define write_c0_watchlo4(val) __write_ulong_c0_register($18, 4, val)
1952 #define write_c0_watchlo5(val) __write_ulong_c0_register($18, 5, val)
1953 #define write_c0_watchlo6(val) __write_ulong_c0_register($18, 6, val)
1954 #define write_c0_watchlo7(val) __write_ulong_c0_register($18, 7, val)
2017 #define read_c0_perfctrl0() __read_32bit_c0_register($25, 0)
2018 #define write_c0_perfctrl0(val) __write_32bit_c0_register($25, 0, val)
2019 #define read_c0_perfcntr0() __read_32bit_c0_register($25, 1)
2020 #define write_c0_perfcntr0(val) __write_32bit_c0_register($25, 1, val)
2021 #define read_c0_perfcntr0_64() __read_64bit_c0_register($25, 1)
2022 #define write_c0_perfcntr0_64(val) __write_64bit_c0_register($25, 1, val)
2023 #define read_c0_perfctrl1() __read_32bit_c0_register($25, 2)
2024 #define write_c0_perfctrl1(val) __write_32bit_c0_register($25, 2, val)
2025 #define read_c0_perfcntr1() __read_32bit_c0_register($25, 3)
2026 #define write_c0_perfcntr1(val) __write_32bit_c0_register($25, 3, val)
2027 #define read_c0_perfcntr1_64() __read_64bit_c0_register($25, 3)
2028 #define write_c0_perfcntr1_64(val) __write_64bit_c0_register($25, 3, val)
2029 #define read_c0_perfctrl2() __read_32bit_c0_register($25, 4)
2030 #define write_c0_perfctrl2(val) __write_32bit_c0_register($25, 4, val)
2031 #define read_c0_perfcntr2() __read_32bit_c0_register($25, 5)
2032 #define write_c0_perfcntr2(val) __write_32bit_c0_register($25, 5, val)
2033 #define read_c0_perfcntr2_64() __read_64bit_c0_register($25, 5)
2034 #define write_c0_perfcntr2_64(val) __write_64bit_c0_register($25, 5, val)
2035 #define read_c0_perfctrl3() __read_32bit_c0_register($25, 6)
2036 #define write_c0_perfctrl3(val) __write_32bit_c0_register($25, 6, val)
2037 #define read_c0_perfcntr3() __read_32bit_c0_register($25, 7)
2038 #define write_c0_perfcntr3(val) __write_32bit_c0_register($25, 7, val)
2039 #define read_c0_perfcntr3_64() __read_64bit_c0_register($25, 7)
2040 #define write_c0_perfcntr3_64(val) __write_64bit_c0_register($25, 7, val)
2436 #define read_gc0_watchlo0() __read_ulong_gc0_register($18, 0)
2437 #define read_gc0_watchlo1() __read_ulong_gc0_register($18, 1)
2438 #define read_gc0_watchlo2() __read_ulong_gc0_register($18, 2)
2439 #define read_gc0_watchlo3() __read_ulong_gc0_register($18, 3)
2440 #define read_gc0_watchlo4() __read_ulong_gc0_register($18, 4)
2441 #define read_gc0_watchlo5() __read_ulong_gc0_register($18, 5)
2442 #define read_gc0_watchlo6() __read_ulong_gc0_register($18, 6)
2443 #define read_gc0_watchlo7() __read_ulong_gc0_register($18, 7)
2444 #define write_gc0_watchlo0(val) __write_ulong_gc0_register($18, 0, val)
2445 #define write_gc0_watchlo1(val) __write_ulong_gc0_register($18, 1, val)
2446 #define write_gc0_watchlo2(val) __write_ulong_gc0_register($18, 2, val)
2447 #define write_gc0_watchlo3(val) __write_ulong_gc0_register($18, 3, val)
2448 #define write_gc0_watchlo4(val) __write_ulong_gc0_register($18, 4, val)
2449 #define write_gc0_watchlo5(val) __write_ulong_gc0_register($18, 5, val)
2450 #define write_gc0_watchlo6(val) __write_ulong_gc0_register($18, 6, val)
2451 #define write_gc0_watchlo7(val) __write_ulong_gc0_register($18, 7, val)
2473 #define read_gc0_perfctrl0() __read_32bit_gc0_register($25, 0)
2474 #define write_gc0_perfctrl0(val) __write_32bit_gc0_register($25, 0, val)
2475 #define read_gc0_perfcntr0() __read_32bit_gc0_register($25, 1)
2476 #define write_gc0_perfcntr0(val) __write_32bit_gc0_register($25, 1, val)
2477 #define read_gc0_perfcntr0_64() __read_64bit_gc0_register($25, 1)
2478 #define write_gc0_perfcntr0_64(val) __write_64bit_gc0_register($25, 1, val)
2479 #define read_gc0_perfctrl1() __read_32bit_gc0_register($25, 2)
2480 #define write_gc0_perfctrl1(val) __write_32bit_gc0_register($25, 2, val)
2481 #define read_gc0_perfcntr1() __read_32bit_gc0_register($25, 3)
2482 #define write_gc0_perfcntr1(val) __write_32bit_gc0_register($25, 3, val)
2483 #define read_gc0_perfcntr1_64() __read_64bit_gc0_register($25, 3)
2484 #define write_gc0_perfcntr1_64(val) __write_64bit_gc0_register($25, 3, val)
2485 #define read_gc0_perfctrl2() __read_32bit_gc0_register($25, 4)
2486 #define write_gc0_perfctrl2(val) __write_32bit_gc0_register($25, 4, val)
2487 #define read_gc0_perfcntr2() __read_32bit_gc0_register($25, 5)
2488 #define write_gc0_perfcntr2(val) __write_32bit_gc0_register($25, 5, val)
2489 #define read_gc0_perfcntr2_64() __read_64bit_gc0_register($25, 5)
2490 #define write_gc0_perfcntr2_64(val) __write_64bit_gc0_register($25, 5, val)
2491 #define read_gc0_perfctrl3() __read_32bit_gc0_register($25, 6)
2492 #define write_gc0_perfctrl3(val) __write_32bit_gc0_register($25, 6, val)
2493 #define read_gc0_perfcntr3() __read_32bit_gc0_register($25, 7)
2494 #define write_gc0_perfcntr3(val) __write_32bit_gc0_register($25, 7, val)
2495 #define read_gc0_perfcntr3_64() __read_64bit_gc0_register($25, 7)
2496 #define write_gc0_perfcntr3_64(val) __write_64bit_gc0_register($25, 7, val)