Lines Matching +full:non +full:- +full:zero
1 /* SPDX-License-Identifier: GPL-2.0-or-later */
10 #include <asm/asm-offsets.h>
17 #include <asm/smp-cps.h>
51 * Set dest to non-zero if the core supports the MT ASE, else zero. If
66 * Set dest to non-zero if the core supports MIPSr6 multithreading
67 * (ie. VPs), else zero. If MIPSr6 multithreading is not supported then
131 /* Skip core-level init if we started up coherent */
135 /* Perform any further required core-level initialisation */
236 /* Set exclusive TC, non-active, master */
242 /* Set TC non-active, non-allocatable */
243 mttc0 zero, CP0_TCSTATUS
267 * mips_cps_get_bootcfg() - retrieve boot configuration pointers
287 * Assume non-contiguous numbering. Perhaps some day we'll need
308 addiu t1, t1, -1
419 * CONFIG3 must exist to be running MT startup - just read it.
433 mttc0 zero, CP0_CAUSE
434 mttc0 zero, CP0_STATUS
444 mttc0 zero, CP0_TCHALT
497 mtc0 zero, CP0_TAGLO, 0
498 mtc0 zero, CP0_TAGHI, 0
499 mtc0 zero, CP0_TAGLO, 2
500 mtc0 zero, CP0_TAGHI, 2
506 /* Detect I-cache line size */
512 /* Detect I-cache size */
519 1: /* At this point t1 == I-cache sets per way */
533 /* Detect D-cache line size */
539 /* Detect D-cache size */
546 1: /* At this point t1 == D-cache sets per way */