Lines Matching +full:3 +full:- +full:n
1 // SPDX-License-Identifier: GPL-2.0-or-later
40 /* skip LDB - never unaligned (index) */
48 /* skip LDB - never unaligned (short) */
56 /* skip STB - never unaligned */
60 /* skip STBY - never unaligned */
61 /* skip STDBY - never unaligned */
100 #define IM(i,n) (((i)>>1&((1<<(n-1))-1))|((i)&1?((0-1L)<<(n-1)):0)) argument
105 #define ERR_NOTHANDLED -1
112 unsigned long saddr = regs->ior; in emulate_ldh()
116 DPRINTF("load " RFMT ":" RFMT " to r%d for 2 bytes\n", in emulate_ldh()
117 regs->isr, regs->ior, toreg); in emulate_ldh()
120 " mtsp %4, %%sr1\n" in emulate_ldh()
121 "1: ldbs 0(%%sr1,%3), %2\n" in emulate_ldh()
122 "2: ldbs 1(%%sr1,%3), %0\n" in emulate_ldh()
123 " depw %2, 23, 24, %0\n" in emulate_ldh()
124 "3: \n" in emulate_ldh()
125 ASM_EXCEPTIONTABLE_ENTRY_EFAULT(1b, 3b, "%1") in emulate_ldh()
126 ASM_EXCEPTIONTABLE_ENTRY_EFAULT(2b, 3b, "%1") in emulate_ldh()
128 : "r" (saddr), "r" (regs->isr) ); in emulate_ldh()
130 DPRINTF("val = " RFMT "\n", val); in emulate_ldh()
133 regs->gr[toreg] = val; in emulate_ldh()
140 unsigned long saddr = regs->ior; in emulate_ldw()
144 DPRINTF("load " RFMT ":" RFMT " to r%d for 4 bytes\n", in emulate_ldw()
145 regs->isr, regs->ior, toreg); in emulate_ldw()
148 " zdep %4,28,2,%2\n" /* r19=(ofs&3)*8 */ in emulate_ldw()
149 " mtsp %5, %%sr1\n" in emulate_ldw()
150 " depw %%r0,31,2,%4\n" in emulate_ldw()
151 "1: ldw 0(%%sr1,%4),%0\n" in emulate_ldw()
152 "2: ldw 4(%%sr1,%4),%3\n" in emulate_ldw()
153 " subi 32,%2,%2\n" in emulate_ldw()
154 " mtctl %2,11\n" in emulate_ldw()
155 " vshd %0,%3,%0\n" in emulate_ldw()
156 "3: \n" in emulate_ldw()
157 ASM_EXCEPTIONTABLE_ENTRY_EFAULT(1b, 3b, "%1") in emulate_ldw()
158 ASM_EXCEPTIONTABLE_ENTRY_EFAULT(2b, 3b, "%1") in emulate_ldw()
160 : "r" (saddr), "r" (regs->isr) ); in emulate_ldw()
162 DPRINTF("val = " RFMT "\n", val); in emulate_ldw()
165 ((__u32*)(regs->fr))[toreg] = val; in emulate_ldw()
167 regs->gr[toreg] = val; in emulate_ldw()
173 unsigned long saddr = regs->ior; in emulate_ldd()
178 DPRINTF("load " RFMT ":" RFMT " to r%d for 8 bytes\n", in emulate_ldd()
179 regs->isr, regs->ior, toreg); in emulate_ldd()
186 " depd,z %2,60,3,%3\n" /* shift=(ofs&7)*8 */ in emulate_ldd()
187 " mtsp %5, %%sr1\n" in emulate_ldd()
188 " depd %%r0,63,3,%2\n" in emulate_ldd()
189 "1: ldd 0(%%sr1,%2),%0\n" in emulate_ldd()
190 "2: ldd 8(%%sr1,%2),%4\n" in emulate_ldd()
191 " subi 64,%3,%3\n" in emulate_ldd()
192 " mtsar %3\n" in emulate_ldd()
193 " shrpd %0,%4,%%sar,%0\n" in emulate_ldd()
194 "3: \n" in emulate_ldd()
195 ASM_EXCEPTIONTABLE_ENTRY_EFAULT(1b, 3b, "%1") in emulate_ldd()
196 ASM_EXCEPTIONTABLE_ENTRY_EFAULT(2b, 3b, "%1") in emulate_ldd()
198 : "r" (regs->isr) ); in emulate_ldd()
201 " zdep %2,29,2,%3\n" /* shift=(ofs&3)*8 */ in emulate_ldd()
202 " mtsp %5, %%sr1\n" in emulate_ldd()
203 " dep %%r0,31,2,%2\n" in emulate_ldd()
204 "1: ldw 0(%%sr1,%2),%0\n" in emulate_ldd()
205 "2: ldw 4(%%sr1,%2),%R0\n" in emulate_ldd()
206 "3: ldw 8(%%sr1,%2),%4\n" in emulate_ldd()
207 " subi 32,%3,%3\n" in emulate_ldd()
208 " mtsar %3\n" in emulate_ldd()
209 " vshd %0,%R0,%0\n" in emulate_ldd()
210 " vshd %R0,%4,%R0\n" in emulate_ldd()
211 "4: \n" in emulate_ldd()
214 ASM_EXCEPTIONTABLE_ENTRY_EFAULT(3b, 4b, "%1") in emulate_ldd()
216 : "r" (regs->isr) ); in emulate_ldd()
219 DPRINTF("val = 0x%llx\n", val); in emulate_ldd()
222 regs->fr[toreg] = val; in emulate_ldd()
224 regs->gr[toreg] = val; in emulate_ldd()
231 unsigned long val = regs->gr[frreg], temp1; in emulate_sth()
237 DPRINTF("store r%d (" RFMT ") to " RFMT ":" RFMT " for 2 bytes\n", frreg, in emulate_sth()
238 val, regs->isr, regs->ior); in emulate_sth()
241 " mtsp %4, %%sr1\n" in emulate_sth()
242 " extrw,u %2, 23, 8, %1\n" in emulate_sth()
243 "1: stb %1, 0(%%sr1, %3)\n" in emulate_sth()
244 "2: stb %2, 1(%%sr1, %3)\n" in emulate_sth()
245 "3: \n" in emulate_sth()
246 ASM_EXCEPTIONTABLE_ENTRY_EFAULT(1b, 3b, "%0") in emulate_sth()
247 ASM_EXCEPTIONTABLE_ENTRY_EFAULT(2b, 3b, "%0") in emulate_sth()
249 : "r" (val), "r" (regs->ior), "r" (regs->isr) ); in emulate_sth()
260 val = ((__u32*)(regs->fr))[frreg]; in emulate_stw()
262 val = regs->gr[frreg]; in emulate_stw()
266 DPRINTF("store r%d (" RFMT ") to " RFMT ":" RFMT " for 4 bytes\n", frreg, in emulate_stw()
267 val, regs->isr, regs->ior); in emulate_stw()
271 " mtsp %3, %%sr1\n" in emulate_stw()
272 " zdep %2, 28, 2, %%r19\n" in emulate_stw()
273 " dep %%r0, 31, 2, %2\n" in emulate_stw()
274 " mtsar %%r19\n" in emulate_stw()
275 " depwi,z -2, %%sar, 32, %%r19\n" in emulate_stw()
276 "1: ldw 0(%%sr1,%2),%%r20\n" in emulate_stw()
277 "2: ldw 4(%%sr1,%2),%%r21\n" in emulate_stw()
278 " vshd %%r0, %1, %%r22\n" in emulate_stw()
279 " vshd %1, %%r0, %%r1\n" in emulate_stw()
280 " and %%r20, %%r19, %%r20\n" in emulate_stw()
281 " andcm %%r21, %%r19, %%r21\n" in emulate_stw()
282 " or %%r22, %%r20, %%r20\n" in emulate_stw()
283 " or %%r1, %%r21, %%r21\n" in emulate_stw()
284 " stw %%r20,0(%%sr1,%2)\n" in emulate_stw()
285 " stw %%r21,4(%%sr1,%2)\n" in emulate_stw()
286 "3: \n" in emulate_stw()
287 ASM_EXCEPTIONTABLE_ENTRY_EFAULT(1b, 3b, "%0") in emulate_stw()
288 ASM_EXCEPTIONTABLE_ENTRY_EFAULT(2b, 3b, "%0") in emulate_stw()
290 : "r" (val), "r" (regs->ior), "r" (regs->isr) in emulate_stw()
301 val = regs->fr[frreg]; in emulate_std()
303 val = regs->gr[frreg]; in emulate_std()
307 DPRINTF("store r%d (0x%016llx) to " RFMT ":" RFMT " for 8 bytes\n", frreg, in emulate_std()
308 val, regs->isr, regs->ior); in emulate_std()
315 " mtsp %3, %%sr1\n" in emulate_std()
316 " depd,z %2, 60, 3, %%r19\n" in emulate_std()
317 " depd %%r0, 63, 3, %2\n" in emulate_std()
318 " mtsar %%r19\n" in emulate_std()
319 " depdi,z -2, %%sar, 64, %%r19\n" in emulate_std()
320 "1: ldd 0(%%sr1,%2),%%r20\n" in emulate_std()
321 "2: ldd 8(%%sr1,%2),%%r21\n" in emulate_std()
322 " shrpd %%r0, %1, %%sar, %%r22\n" in emulate_std()
323 " shrpd %1, %%r0, %%sar, %%r1\n" in emulate_std()
324 " and %%r20, %%r19, %%r20\n" in emulate_std()
325 " andcm %%r21, %%r19, %%r21\n" in emulate_std()
326 " or %%r22, %%r20, %%r20\n" in emulate_std()
327 " or %%r1, %%r21, %%r21\n" in emulate_std()
328 "3: std %%r20,0(%%sr1,%2)\n" in emulate_std()
329 "4: std %%r21,8(%%sr1,%2)\n" in emulate_std()
330 "5: \n" in emulate_std()
333 ASM_EXCEPTIONTABLE_ENTRY_EFAULT(3b, 5b, "%0") in emulate_std()
336 : "r" (val), "r" (regs->ior), "r" (regs->isr) in emulate_std()
341 " mtsp %3, %%sr1\n" in emulate_std()
342 " zdep %R1, 29, 2, %%r19\n" in emulate_std()
343 " dep %%r0, 31, 2, %2\n" in emulate_std()
344 " mtsar %%r19\n" in emulate_std()
345 " zvdepi -2, 32, %%r19\n" in emulate_std()
346 "1: ldw 0(%%sr1,%2),%%r20\n" in emulate_std()
347 "2: ldw 8(%%sr1,%2),%%r21\n" in emulate_std()
348 " vshd %1, %R1, %%r1\n" in emulate_std()
349 " vshd %%r0, %1, %1\n" in emulate_std()
350 " vshd %R1, %%r0, %R1\n" in emulate_std()
351 " and %%r20, %%r19, %%r20\n" in emulate_std()
352 " andcm %%r21, %%r19, %%r21\n" in emulate_std()
353 " or %1, %%r20, %1\n" in emulate_std()
354 " or %R1, %%r21, %R1\n" in emulate_std()
355 "3: stw %1,0(%%sr1,%2)\n" in emulate_std()
356 "4: stw %%r1,4(%%sr1,%2)\n" in emulate_std()
357 "5: stw %R1,8(%%sr1,%2)\n" in emulate_std()
358 "6: \n" in emulate_std()
361 ASM_EXCEPTIONTABLE_ENTRY_EFAULT(3b, 6b, "%0") in emulate_std()
365 : "r" (val), "r" (regs->ior), "r" (regs->isr) in emulate_std()
376 unsigned long newbase = R1(regs->iir)?regs->gr[R1(regs->iir)]:0; in handle_unaligned()
384 if (current->thread.flags & PARISC_UAC_SIGBUS) { in handle_unaligned()
388 if (!(current->thread.flags & PARISC_UAC_NOPRINT) && in handle_unaligned()
391 " at ip " RFMT " (iir " RFMT ")\n", in handle_unaligned()
392 current->comm, task_pid_nr(current), regs->ior, in handle_unaligned()
393 regs->iaoq[0], regs->iir); in handle_unaligned()
403 if (!(current->thread.flags & PARISC_UAC_NOPRINT) && in handle_unaligned()
407 "(iir " RFMT ")\n", in handle_unaligned()
408 regs->ior, (void *)regs->iaoq[0], regs->iir); in handle_unaligned()
411 /* handle modification - OK, it's ugly, see the instruction manual */ in handle_unaligned()
412 switch (MAJOR_OP(regs->iir)) in handle_unaligned()
417 if (regs->iir&0x20) in handle_unaligned()
420 if (regs->iir&0x1000) /* short loads */ in handle_unaligned()
421 if (regs->iir&0x200) in handle_unaligned()
422 newbase += IM5_3(regs->iir); in handle_unaligned()
424 newbase += IM5_2(regs->iir); in handle_unaligned()
425 else if (regs->iir&0x2000) /* scaled indexed */ in handle_unaligned()
428 switch (regs->iir & OPCODE1_MASK) in handle_unaligned()
436 shift= 3; break; in handle_unaligned()
438 newbase += (R2(regs->iir)?regs->gr[R2(regs->iir)]:0)<<shift; in handle_unaligned()
440 newbase += (R2(regs->iir)?regs->gr[R2(regs->iir)]:0); in handle_unaligned()
446 newbase += IM14(regs->iir); in handle_unaligned()
450 if (regs->iir&8) in handle_unaligned()
453 newbase += IM14(regs->iir&~0xe); in handle_unaligned()
459 newbase += IM14(regs->iir&6); in handle_unaligned()
463 if (regs->iir&4) in handle_unaligned()
466 newbase += IM14(regs->iir&~4); in handle_unaligned()
472 switch (regs->iir & OPCODE1_MASK) in handle_unaligned()
476 ret = emulate_ldh(regs, R3(regs->iir)); in handle_unaligned()
483 ret = emulate_ldw(regs, R3(regs->iir), 0); in handle_unaligned()
487 ret = emulate_sth(regs, R2(regs->iir)); in handle_unaligned()
492 ret = emulate_stw(regs, R2(regs->iir), 0); in handle_unaligned()
500 ret = emulate_ldd(regs, R3(regs->iir), 0); in handle_unaligned()
505 ret = emulate_std(regs, R2(regs->iir), 0); in handle_unaligned()
513 ret = emulate_ldw(regs, FR3(regs->iir), 1); in handle_unaligned()
518 ret = emulate_ldd(regs, R3(regs->iir), 1); in handle_unaligned()
525 ret = emulate_stw(regs, FR3(regs->iir), 1); in handle_unaligned()
530 ret = emulate_std(regs, R3(regs->iir), 1); in handle_unaligned()
540 switch (regs->iir & OPCODE2_MASK) in handle_unaligned()
543 ret = emulate_ldd(regs,R2(regs->iir),1); in handle_unaligned()
546 ret = emulate_std(regs, R2(regs->iir),1); in handle_unaligned()
550 ret = emulate_ldd(regs, R2(regs->iir),0); in handle_unaligned()
553 ret = emulate_std(regs, R2(regs->iir),0); in handle_unaligned()
557 switch (regs->iir & OPCODE3_MASK) in handle_unaligned()
560 ret = emulate_ldw(regs, R2(regs->iir), 1); in handle_unaligned()
563 ret = emulate_ldw(regs, R2(regs->iir), 0); in handle_unaligned()
567 ret = emulate_stw(regs, R2(regs->iir),1); in handle_unaligned()
570 ret = emulate_stw(regs, R2(regs->iir),0); in handle_unaligned()
573 switch (regs->iir & OPCODE4_MASK) in handle_unaligned()
576 ret = emulate_ldh(regs, R2(regs->iir)); in handle_unaligned()
580 ret = emulate_ldw(regs, R2(regs->iir),0); in handle_unaligned()
583 ret = emulate_sth(regs, R2(regs->iir)); in handle_unaligned()
587 ret = emulate_stw(regs, R2(regs->iir),0); in handle_unaligned()
591 if (ret == 0 && modify && R1(regs->iir)) in handle_unaligned()
592 regs->gr[R1(regs->iir)] = newbase; in handle_unaligned()
596 printk(KERN_CRIT "Not-handled unaligned insn 0x%08lx\n", regs->iir); in handle_unaligned()
598 DPRINTF("ret = %d\n", ret); in handle_unaligned()
610 printk(KERN_CRIT "Unaligned handler failed, ret = %d\n", ret); in handle_unaligned()
613 if (ret == -EFAULT) in handle_unaligned()
616 (void __user *)regs->ior); in handle_unaligned()
623 (void __user *)regs->ior); in handle_unaligned()
630 regs->gr[0]|=PSW_N; in handle_unaligned()
646 switch (regs->iir & OPCODE1_MASK) { in check_unaligned()
660 align_mask = 3UL; in check_unaligned()
664 switch (regs->iir & OPCODE4_MASK) { in check_unaligned()
673 align_mask = 3UL; in check_unaligned()
679 return (int)(regs->ior & align_mask); in check_unaligned()