Lines Matching +full:next +full:- +full:level +full:- +full:cache
4 * Copyright 2012 - 2015 Freescale Semiconductor Inc.
35 /dts-v1/;
41 #address-cells = <2>;
42 #size-cells = <2>;
43 interrupt-parent = <&mpic>;
87 #address-cells = <1>;
88 #size-cells = <0>;
94 next-level-cache = <&L2_1>;
95 fsl,portid-mapping = <0x80000000>;
101 next-level-cache = <&L2_1>;
102 fsl,portid-mapping = <0x80000000>;
108 next-level-cache = <&L2_1>;
109 fsl,portid-mapping = <0x80000000>;
115 next-level-cache = <&L2_1>;
116 fsl,portid-mapping = <0x80000000>;
122 next-level-cache = <&L2_2>;
123 fsl,portid-mapping = <0x40000000>;
129 next-level-cache = <&L2_2>;
130 fsl,portid-mapping = <0x40000000>;
136 next-level-cache = <&L2_2>;
137 fsl,portid-mapping = <0x40000000>;
143 next-level-cache = <&L2_2>;
144 fsl,portid-mapping = <0x40000000>;
150 next-level-cache = <&L2_3>;
151 fsl,portid-mapping = <0x20000000>;
157 next-level-cache = <&L2_3>;
158 fsl,portid-mapping = <0x20000000>;
164 next-level-cache = <&L2_3>;
165 fsl,portid-mapping = <0x20000000>;
171 next-level-cache = <&L2_3>;
172 fsl,portid-mapping = <0x20000000>;