Lines Matching +full:local +full:- +full:bd +full:- +full:address
1 /* SPDX-License-Identifier: GPL-2.0 */
27 /* Device sub-block and page codes.
72 /* CPM2-specific opcodes (see cpm.h for common opcodes)
85 /* Export the base address of the communication processor registers
153 * get some microcode patches :-).
154 * The parameter ram space for the SMCs is fifty-some bytes, and
164 ushort smc_rbase; /* Rx Buffer descriptor base address */
165 ushort smc_tbase; /* Tx Buffer descriptor base address */
306 ushort scc_rbase; /* Rx Buffer descriptor base address */
307 ushort scc_tbase; /* Tx Buffer descriptor base address */
348 ushort sen_maxb; /* Max BD byte count */
349 ushort sen_gaddr1; /* Group address filter */
353 uint sen_tbuf0data0; /* Save area 0 - current frame */
354 uint sen_tbuf0data1; /* Save area 1 - current frame */
358 ushort sen_paddrh; /* physical address (MSB) */
360 ushort sen_paddrl; /* physical address (LSB) */
362 ushort sen_rfbdptr; /* Rx first BD pointer */
363 ushort sen_tfbdptr; /* Tx first BD pointer */
364 ushort sen_tlbdptr; /* Tx last BD pointer */
365 uint sen_tbuf1data0; /* Save area 0 - current frame */
366 uint sen_tbuf1data1; /* Save area 1 - current frame */
371 ushort sen_iaddr1; /* Individual address filter */
380 ushort sen_taddrh; /* temp address (MSB) */
382 ushort sen_taddrl; /* temp address (LSB) */
425 ushort scc_uaddr1; /* UART address character 1 */
426 ushort scc_uaddr2; /* UART address character 2 */
519 uint fcc_rbase; /* Receive BD base */
524 uint fcc_tbase; /* Transmit BD base */
528 uint fcc_rbptr; /* Rx BD Internal buf pointer */
529 uint fcc_tbptr; /* Tx BD Internal buf pointer */
541 uint fen_camptr; /* CAM address */
551 uint fen_gaddrh; /* Group address filter, high 32-bits */
552 uint fen_gaddrl; /* Group address filter, low 32-bits */
557 ushort fen_paddrh; /* MAC address */
560 ushort fen_ibdcount; /* Internal BD counter */
561 ushort fen_ibdstart; /* Internal BD start pointer */
562 ushort fen_ibdend; /* Internal BD end pointer */
565 uint fen_iaddrh; /* Individual address filter */
568 ushort fen_taddrh; /* Filter transfer MAC address */
574 ushort fen_maxb; /* maximum BD count */
614 #define FCC_PSMR_LPB ((uint)0x10000000) /* Local protect. 1 = FDX */
623 #define FCC_PSMR_ENCRC ((uint)0x00000080) /* Use 32-bit CRC */
628 ushort iic_rbase; /* Rx Buffer descriptor base address */
629 ushort iic_tbase; /* Tx Buffer descriptor base address */
648 ushort ibase; /* IDMA buffer descriptor table base address */
651 ushort dpr_buf; /* IDMA transfer buffer base address */
653 ushort ss_max; /* steady-state maximum transfer size */
660 ushort ret_add; /* return address when working in ERM=1 mode */
666 u_char res1[20]; /* pad to 64-byte length */
671 #define IDMA_DCM_FB ((ushort)0x8000) /* fly-by mode */
675 #define IDMA_DCM_DMA_WRAP_64 ((ushort)0x0000) /* 64-byte DMA xfer buffer */
676 #define IDMA_DCM_DMA_WRAP_128 ((ushort)0x0040) /* 128-byte DMA xfer buffer */
677 #define IDMA_DCM_DMA_WRAP_256 ((ushort)0x0080) /* 256-byte DMA xfer buffer */
678 #define IDMA_DCM_DMA_WRAP_512 ((ushort)0x00c0) /* 512-byte DMA xfer buffer */
679 #define IDMA_DCM_DMA_WRAP_1024 ((ushort)0x0100) /* 1024-byte DMA xfer buffer */
680 #define IDMA_DCM_DMA_WRAP_2048 ((ushort)0x0140) /* 2048-byte DMA xfer buffer */
686 #define IDMA_DCM_SD_MEM2MEM ((ushort)0x0000) /* memory-to-memory xfer */
687 #define IDMA_DCM_SD_PER2MEM ((ushort)0x0002) /* peripheral-to-memory xfer */
688 #define IDMA_DCM_SD_MEM2PER ((ushort)0x0001) /* memory-to-peripheral xfer */
709 #define IDMA_BD_DBO_LE ((uint)0x00040000) /* little-end dest byte order */
710 #define IDMA_BD_DBO_BE ((uint)0x00080000) /* big-end dest byte order */
713 #define IDMA_BD_SBO_LE ((uint)0x00000800) /* little-end src byte order */
714 #define IDMA_BD_SBO_BE ((uint)0x00001000) /* big-end src byte order */
717 /* per-channel IDMA registers
774 /*-----------------------------------------------------------------------
775 * CMXFCR - CMX FCC Clock Route Register
841 /*-----------------------------------------------------------------------
842 * CMXSCR - CMX SCC Clock Route Register
933 /*-----------------------------------------------------------------------
934 * SIUMCR - SIU Module Configuration Register 4-31
941 #define SIUMCR_DPPC01 0x04000000 /* - " - */
942 #define SIUMCR_DPPC10 0x08000000 /* - " - */
943 #define SIUMCR_DPPC11 0x0c000000 /* - " - */
945 #define SIUMCR_L2CPC01 0x01000000 /* - " - */
946 #define SIUMCR_L2CPC10 0x02000000 /* - " - */
947 #define SIUMCR_L2CPC11 0x03000000 /* - " - */
948 #define SIUMCR_LBPC00 0x00000000 /* Local Bus Pins Configuration */
949 #define SIUMCR_LBPC01 0x00400000 /* - " - */
950 #define SIUMCR_LBPC10 0x00800000 /* - " - */
951 #define SIUMCR_LBPC11 0x00c00000 /* - " - */
952 #define SIUMCR_APPC00 0x00000000 /* Address Parity Pins Configuration*/
953 #define SIUMCR_APPC01 0x00100000 /* - " - */
954 #define SIUMCR_APPC10 0x00200000 /* - " - */
955 #define SIUMCR_APPC11 0x00300000 /* - " - */
957 #define SIUMCR_CS10PC01 0x00040000 /* - " - */
958 #define SIUMCR_CS10PC10 0x00080000 /* - " - */
959 #define SIUMCR_CS10PC11 0x000c0000 /* - " - */
961 #define SIUMCR_BCTLC01 0x00010000 /* - " - */
962 #define SIUMCR_BCTLC10 0x00020000 /* - " - */
963 #define SIUMCR_BCTLC11 0x00030000 /* - " - */
965 #define SIUMCR_MMR01 0x00004000 /* - " - */
966 #define SIUMCR_MMR10 0x00008000 /* - " - */
967 #define SIUMCR_MMR11 0x0000c000 /* - " - */
970 /*-----------------------------------------------------------------------
971 * SCCR - System Clock Control Register 9-8
985 * in order to use clock-computing stuff below for the FCC x
989 #define PC_CLK(x) ((uint)(1<<(x-1))) /* FCC CLK I/O ports */
991 #define CMXFCR_RF1CS(x) ((uint)((x-5)<<27)) /* FCC1 Receive Clock Source */
992 #define CMXFCR_TF1CS(x) ((uint)((x-5)<<24)) /* FCC1 Transmit Clock Source */
993 #define CMXFCR_RF2CS(x) ((uint)((x-9)<<19)) /* FCC2 Receive Clock Source */
994 #define CMXFCR_TF2CS(x) ((uint)((x-9)<<16)) /* FCC2 Transmit Clock Source */
995 #define CMXFCR_RF3CS(x) ((uint)((x-9)<<11)) /* FCC3 Receive Clock Source */
996 #define CMXFCR_TF3CS(x) ((uint)((x-9)<<8)) /* FCC3 Transmit Clock Source */