Lines Matching +full:rmii +full:- +full:clk +full:- +full:internal
1 /* SPDX-License-Identifier: GPL-2.0 */
7 * All CPM control and status is available through the CPM2 internal
27 /* Device sub-block and page codes.
72 /* CPM2-specific opcodes (see cpm.h for common opcodes)
106 extern void __cpm2_setbrg(uint brg, uint rate, uint clk, int div16, int src);
153 * get some microcode patches :-).
154 * The parameter ram space for the SMCs is fifty-some bytes, and
169 uint smc_rstate; /* Internal */
170 uint smc_idp; /* Internal */
171 ushort smc_rbptr; /* Internal */
172 ushort smc_ibc; /* Internal */
173 uint smc_rxtmp; /* Internal */
174 uint smc_tstate; /* Internal */
175 uint smc_tdp; /* Internal */
176 ushort smc_tbptr; /* Internal */
177 ushort smc_tbc; /* Internal */
178 uint smc_txtmp; /* Internal */
188 /* SMC uart mode register (Internal memory map).
311 uint scc_rstate; /* Internal */
312 uint scc_idp; /* Internal */
313 ushort scc_rbptr; /* Internal */
314 ushort scc_ibc; /* Internal */
315 uint scc_rxtmp; /* Internal */
316 uint scc_tstate; /* Internal */
317 uint scc_tdp; /* Internal */
318 ushort scc_tbptr; /* Internal */
319 ushort scc_tbc; /* Internal */
320 uint scc_txtmp; /* Internal */
321 uint scc_rcrc; /* Internal */
322 uint scc_tcrc; /* Internal */
353 uint sen_tbuf0data0; /* Save area 0 - current frame */
354 uint sen_tbuf0data1; /* Save area 1 - current frame */
355 uint sen_tbuf0rba; /* Internal */
356 uint sen_tbuf0crc; /* Internal */
357 ushort sen_tbuf0bcnt; /* Internal */
365 uint sen_tbuf1data0; /* Save area 0 - current frame */
366 uint sen_tbuf1data1; /* Save area 1 - current frame */
367 uint sen_tbuf1rba; /* Internal */
368 uint sen_tbuf1crc; /* Internal */
369 ushort sen_tbuf1bcnt; /* Internal */
514 ushort fcc_riptr; /* Rx Internal temp pointer */
515 ushort fcc_tiptr; /* Tx Internal temp pointer */
522 uint fcc_rdptr; /* RxBD internal data pointer */
527 uint fcc_tdptr; /* TxBD internal data pointer */
528 uint fcc_rbptr; /* Rx BD Internal buf pointer */
529 uint fcc_tbptr; /* Tx BD Internal buf pointer */
540 uint fen_statbuf; /* Internal status buffer */
551 uint fen_gaddrh; /* Group address filter, high 32-bits */
552 uint fen_gaddrl; /* Group address filter, low 32-bits */
560 ushort fen_ibdcount; /* Internal BD counter */
561 ushort fen_ibdstart; /* Internal BD start pointer */
562 ushort fen_ibdend; /* Internal BD end pointer */
563 ushort fen_txlen; /* Internal Tx frame length counter */
564 uint fen_ibdbase[8]; /* Internal use */
577 ushort fen_maxd; /* internal max DMA count */
578 ushort fen_dmacnt; /* internal DMA counter */
593 uint fen_cambuf; /* Internal CAM buffer pointer */
623 #define FCC_PSMR_ENCRC ((uint)0x00000080) /* Use 32-bit CRC */
633 uint iic_rstate; /* Internal */
634 uint iic_rdp; /* Internal */
635 ushort iic_rbptr; /* Internal */
636 ushort iic_rbc; /* Internal */
637 uint iic_rxtmp; /* Internal */
638 uint iic_tstate; /* Internal */
639 uint iic_tdp; /* Internal */
640 ushort iic_tbptr; /* Internal */
641 ushort iic_tbc; /* Internal */
642 uint iic_txtmp; /* Internal */
652 ushort buf_inv; /* internal buffer inventory */
653 ushort ss_max; /* steady-state maximum transfer size */
654 ushort dpr_in_ptr; /* write pointer inside the internal buffer */
656 ushort dpr_out_ptr; /* read pointer inside the internal buffer */
662 uint bd_cnt; /* internal byte count */
663 uint s_ptr; /* source internal data pointer */
664 uint d_ptr; /* destination internal data pointer */
665 uint istate; /* internal state */
666 u_char res1[20]; /* pad to 64-byte length */
671 #define IDMA_DCM_FB ((ushort)0x8000) /* fly-by mode */
675 #define IDMA_DCM_DMA_WRAP_64 ((ushort)0x0000) /* 64-byte DMA xfer buffer */
676 #define IDMA_DCM_DMA_WRAP_128 ((ushort)0x0040) /* 128-byte DMA xfer buffer */
677 #define IDMA_DCM_DMA_WRAP_256 ((ushort)0x0080) /* 256-byte DMA xfer buffer */
678 #define IDMA_DCM_DMA_WRAP_512 ((ushort)0x00c0) /* 512-byte DMA xfer buffer */
679 #define IDMA_DCM_DMA_WRAP_1024 ((ushort)0x0100) /* 1024-byte DMA xfer buffer */
680 #define IDMA_DCM_DMA_WRAP_2048 ((ushort)0x0140) /* 2048-byte DMA xfer buffer */
686 #define IDMA_DCM_SD_MEM2MEM ((ushort)0x0000) /* memory-to-memory xfer */
687 #define IDMA_DCM_SD_PER2MEM ((ushort)0x0002) /* peripheral-to-memory xfer */
688 #define IDMA_DCM_SD_MEM2PER ((ushort)0x0001) /* memory-to-peripheral xfer */
709 #define IDMA_BD_DBO_LE ((uint)0x00040000) /* little-end dest byte order */
710 #define IDMA_BD_DBO_BE ((uint)0x00080000) /* big-end dest byte order */
713 #define IDMA_BD_SBO_LE ((uint)0x00000800) /* little-end src byte order */
714 #define IDMA_BD_SBO_BE ((uint)0x00001000) /* big-end src byte order */
717 /* per-channel IDMA registers
774 /*-----------------------------------------------------------------------
775 * CMXFCR - CMX FCC Clock Route Register
841 /*-----------------------------------------------------------------------
842 * CMXSCR - CMX SCC Clock Route Register
933 /*-----------------------------------------------------------------------
934 * SIUMCR - SIU Module Configuration Register 4-31
941 #define SIUMCR_DPPC01 0x04000000 /* - " - */
942 #define SIUMCR_DPPC10 0x08000000 /* - " - */
943 #define SIUMCR_DPPC11 0x0c000000 /* - " - */
945 #define SIUMCR_L2CPC01 0x01000000 /* - " - */
946 #define SIUMCR_L2CPC10 0x02000000 /* - " - */
947 #define SIUMCR_L2CPC11 0x03000000 /* - " - */
949 #define SIUMCR_LBPC01 0x00400000 /* - " - */
950 #define SIUMCR_LBPC10 0x00800000 /* - " - */
951 #define SIUMCR_LBPC11 0x00c00000 /* - " - */
953 #define SIUMCR_APPC01 0x00100000 /* - " - */
954 #define SIUMCR_APPC10 0x00200000 /* - " - */
955 #define SIUMCR_APPC11 0x00300000 /* - " - */
957 #define SIUMCR_CS10PC01 0x00040000 /* - " - */
958 #define SIUMCR_CS10PC10 0x00080000 /* - " - */
959 #define SIUMCR_CS10PC11 0x000c0000 /* - " - */
961 #define SIUMCR_BCTLC01 0x00010000 /* - " - */
962 #define SIUMCR_BCTLC10 0x00020000 /* - " - */
963 #define SIUMCR_BCTLC11 0x00030000 /* - " - */
965 #define SIUMCR_MMR01 0x00004000 /* - " - */
966 #define SIUMCR_MMR10 0x00008000 /* - " - */
967 #define SIUMCR_MMR11 0x0000c000 /* - " - */
970 /*-----------------------------------------------------------------------
971 * SCCR - System Clock Control Register 9-8
982 #define FCC_PSMR_RMII ((uint)0x00020000) /* Use RMII interface */
985 * in order to use clock-computing stuff below for the FCC x
989 #define PC_CLK(x) ((uint)(1<<(x-1))) /* FCC CLK I/O ports */
991 #define CMXFCR_RF1CS(x) ((uint)((x-5)<<27)) /* FCC1 Receive Clock Source */
992 #define CMXFCR_TF1CS(x) ((uint)((x-5)<<24)) /* FCC1 Transmit Clock Source */
993 #define CMXFCR_RF2CS(x) ((uint)((x-9)<<19)) /* FCC2 Receive Clock Source */
994 #define CMXFCR_TF2CS(x) ((uint)((x-9)<<16)) /* FCC2 Transmit Clock Source */
995 #define CMXFCR_RF3CS(x) ((uint)((x-9)<<11)) /* FCC3 Receive Clock Source */
996 #define CMXFCR_TF3CS(x) ((uint)((x-9)<<8)) /* FCC3 Transmit Clock Source */