Lines Matching +full:max +full:- +full:outbound +full:- +full:regions
2 * PCI / PCI-X / PCI-Express support for 4xx parts
30 #include <asm/pci-bridge.h>
33 #include <asm/dcr-regs.h>
62 if (dev->devfn != 0 || dev->bus->self != NULL) in fixup_ppc4xx_pci_bridge()
65 hose = pci_bus_to_host(dev->bus); in fixup_ppc4xx_pci_bridge()
69 if (!of_device_is_compatible(hose->dn, "ibm,plb-pciex") && in fixup_ppc4xx_pci_bridge()
70 !of_device_is_compatible(hose->dn, "ibm,plb-pcix") && in fixup_ppc4xx_pci_bridge()
71 !of_device_is_compatible(hose->dn, "ibm,plb-pci")) in fixup_ppc4xx_pci_bridge()
74 if (of_device_is_compatible(hose->dn, "ibm,plb440epx-pci") || in fixup_ppc4xx_pci_bridge()
75 of_device_is_compatible(hose->dn, "ibm,plb440grx-pci")) { in fixup_ppc4xx_pci_bridge()
76 hose->indirect_type |= PPC_INDIRECT_TYPE_BROKEN_MRM; in fixup_ppc4xx_pci_bridge()
83 r->start = r->end = 0; in fixup_ppc4xx_pci_bridge()
84 r->flags = 0; in fixup_ppc4xx_pci_bridge()
101 res->start = 0; in ppc4xx_parse_dma_ranges()
103 res->end = size - 1; in ppc4xx_parse_dma_ranges()
104 res->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH; in ppc4xx_parse_dma_ranges()
106 if (of_pci_dma_range_parser_init(&parser, hose->dn)) in ppc4xx_parse_dma_ranges()
127 " 0x%016llx...0x%016llx -> 0x%016llx\n", in ppc4xx_parse_dma_ranges()
128 hose->dn, in ppc4xx_parse_dma_ranges()
129 pci_addr, pci_addr + size - 1, cpu_addr); in ppc4xx_parse_dma_ranges()
135 res->flags &= ~IORESOURCE_PREFETCH; in ppc4xx_parse_dma_ranges()
139 res->start = pci_addr; in ppc4xx_parse_dma_ranges()
143 res->end = 0xffffffff; in ppc4xx_parse_dma_ranges()
145 res->end = res->start + size - 1; in ppc4xx_parse_dma_ranges()
150 if (dma_offset_set && pci_dram_offset != res->start) { in ppc4xx_parse_dma_ranges()
151 printk(KERN_ERR "%pOF: dma-ranges(s) mismatch\n", hose->dn); in ppc4xx_parse_dma_ranges()
152 return -ENXIO; in ppc4xx_parse_dma_ranges()
159 printk(KERN_ERR "%pOF: dma-ranges too small " in ppc4xx_parse_dma_ranges()
161 hose->dn, size, (u64)total_memory); in ppc4xx_parse_dma_ranges()
162 return -ENXIO; in ppc4xx_parse_dma_ranges()
166 if ((size & (size - 1)) != 0 || in ppc4xx_parse_dma_ranges()
167 (res->start & (size - 1)) != 0) { in ppc4xx_parse_dma_ranges()
168 printk(KERN_ERR "%pOF: dma-ranges unaligned\n", hose->dn); in ppc4xx_parse_dma_ranges()
169 return -ENXIO; in ppc4xx_parse_dma_ranges()
175 if (res->end > 0xffffffff && in ppc4xx_parse_dma_ranges()
176 !(of_device_is_compatible(hose->dn, "ibm,plb-pciex-460sx") in ppc4xx_parse_dma_ranges()
177 || of_device_is_compatible(hose->dn, "ibm,plb-pciex-476fpe"))) { in ppc4xx_parse_dma_ranges()
178 printk(KERN_ERR "%pOF: dma-ranges outside of 32 bits space\n", in ppc4xx_parse_dma_ranges()
179 hose->dn); in ppc4xx_parse_dma_ranges()
180 return -ENXIO; in ppc4xx_parse_dma_ranges()
184 pci_dram_offset = res->start; in ppc4xx_parse_dma_ranges()
185 hose->dma_window_base_cur = res->start; in ppc4xx_parse_dma_ranges()
186 hose->dma_window_size = resource_size(res); in ppc4xx_parse_dma_ranges()
191 (unsigned long long)hose->dma_window_base_cur); in ppc4xx_parse_dma_ranges()
193 (unsigned long long)hose->dma_window_size); in ppc4xx_parse_dma_ranges()
212 * 32-bit of incoming PLB addresses. The top 4 bits of the 36-bit in ppc4xx_setup_one_pci_PMM()
217 * programming the chip. That means the device-tree has to be right in ppc4xx_setup_one_pci_PMM()
229 size < 0x1000 || (plb_addr & (size - 1)) != 0) { in ppc4xx_setup_one_pci_PMM()
230 printk(KERN_WARNING "%pOF: Resource out of range\n", hose->dn); in ppc4xx_setup_one_pci_PMM()
231 return -1; in ppc4xx_setup_one_pci_PMM()
253 /* Setup outbound memory windows */ in ppc4xx_configure_pci_PMMs()
255 struct resource *res = &hose->mem_resources[i]; in ppc4xx_configure_pci_PMMs()
256 resource_size_t offset = hose->mem_offset[i]; in ppc4xx_configure_pci_PMMs()
259 if (!(res->flags & IORESOURCE_MEM)) in ppc4xx_configure_pci_PMMs()
262 printk(KERN_WARNING "%pOF: Too many ranges\n", hose->dn); in ppc4xx_configure_pci_PMMs()
268 res->start, in ppc4xx_configure_pci_PMMs()
269 res->start - offset, in ppc4xx_configure_pci_PMMs()
271 res->flags, in ppc4xx_configure_pci_PMMs()
278 if (res->start == offset) in ppc4xx_configure_pci_PMMs()
284 if (j <= 2 && !found_isa_hole && hose->isa_mem_size) in ppc4xx_configure_pci_PMMs()
285 if (ppc4xx_setup_one_pci_PMM(hose, reg, hose->isa_mem_phys, 0, in ppc4xx_configure_pci_PMMs()
286 hose->isa_mem_size, 0, j) == 0) in ppc4xx_configure_pci_PMMs()
288 hose->dn); in ppc4xx_configure_pci_PMMs()
307 early_write_config_dword(hose, hose->first_busno, 0, in ppc4xx_configure_pci_PTMs()
308 PCI_BASE_ADDRESS_1, res->start); in ppc4xx_configure_pci_PTMs()
309 early_write_config_dword(hose, hose->first_busno, 0, in ppc4xx_configure_pci_PTMs()
311 early_write_config_word(hose, hose->first_busno, 0, in ppc4xx_configure_pci_PTMs()
328 printk(KERN_INFO "%pOF: Port disabled via device-tree\n", np); in ppc4xx_probe_pci_bridge()
350 bus_range = of_get_property(np, "bus-range", NULL); in ppc4xx_probe_pci_bridge()
364 hose->first_busno = bus_range ? bus_range[0] : 0x0; in ppc4xx_probe_pci_bridge()
365 hose->last_busno = bus_range ? bus_range[1] : 0xff; in ppc4xx_probe_pci_bridge()
377 /* Parse outbound mapping resources */ in ppc4xx_probe_pci_bridge()
384 /* Configure outbound ranges POMs */ in ppc4xx_probe_pci_bridge()
402 * 4xx PCI-X part
416 (plb_addr & (size - 1)) != 0) { in ppc4xx_setup_one_pcix_POM()
418 hose->dn); in ppc4xx_setup_one_pcix_POM()
419 return -1; in ppc4xx_setup_one_pcix_POM()
452 /* Setup outbound memory windows */ in ppc4xx_configure_pcix_POMs()
454 struct resource *res = &hose->mem_resources[i]; in ppc4xx_configure_pcix_POMs()
455 resource_size_t offset = hose->mem_offset[i]; in ppc4xx_configure_pcix_POMs()
458 if (!(res->flags & IORESOURCE_MEM)) in ppc4xx_configure_pcix_POMs()
461 printk(KERN_WARNING "%pOF: Too many ranges\n", hose->dn); in ppc4xx_configure_pcix_POMs()
467 res->start, in ppc4xx_configure_pcix_POMs()
468 res->start - offset, in ppc4xx_configure_pcix_POMs()
470 res->flags, in ppc4xx_configure_pcix_POMs()
477 if (res->start == offset) in ppc4xx_configure_pcix_POMs()
483 if (j <= 1 && !found_isa_hole && hose->isa_mem_size) in ppc4xx_configure_pcix_POMs()
484 if (ppc4xx_setup_one_pcix_POM(hose, reg, hose->isa_mem_phys, 0, in ppc4xx_configure_pcix_POMs()
485 hose->isa_mem_size, 0, j) == 0) in ppc4xx_configure_pcix_POMs()
487 hose->dn); in ppc4xx_configure_pcix_POMs()
506 if (res->flags & IORESOURCE_PREFETCH) in ppc4xx_configure_pcix_PIMs()
516 writel(res->start, reg + PCIX0_BAR0L); in ppc4xx_configure_pcix_PIMs()
532 printk(KERN_ERR "%pOF: Can't get PCI-X config register base !", in ppc4xx_probe_pcix_bridge()
538 printk(KERN_ERR "%pOF: Can't get PCI-X internal register base !", in ppc4xx_probe_pcix_bridge()
544 big_pim = of_property_read_bool(np, "large-inbound-windows"); in ppc4xx_probe_pcix_bridge()
547 msi = of_property_read_bool(np, "enable-msi-hole"); in ppc4xx_probe_pcix_bridge()
553 bus_range = of_get_property(np, "bus-range", NULL); in ppc4xx_probe_pcix_bridge()
567 hose->first_busno = bus_range ? bus_range[0] : 0x0; in ppc4xx_probe_pcix_bridge()
568 hose->last_busno = bus_range ? bus_range[1] : 0xff; in ppc4xx_probe_pcix_bridge()
586 /* Parse outbound mapping resources */ in ppc4xx_probe_pcix_bridge()
593 /* Configure outbound ranges POMs */ in ppc4xx_probe_pcix_bridge()
613 * 4xx PCI-Express part
617 * ibm,plb-pciex-440spe
618 * ibm,plb-pciex-405ex
619 * ibm,plb-pciex-460ex
665 while(timeout_ms--) { in ppc4xx_pciex_wait_on_sdr()
666 val = mfdcri(SDR0, port->sdr_base + sdr_offset); in ppc4xx_pciex_wait_on_sdr()
669 port->index, sdr_offset, timeout_ms, val); in ppc4xx_pciex_wait_on_sdr()
674 return -1; in ppc4xx_pciex_wait_on_sdr()
682 port->index); in ppc4xx_pciex_port_reset_sdr()
683 return -1; in ppc4xx_pciex_port_reset_sdr()
691 printk(KERN_INFO "PCIE%d: Checking link...\n", port->index); in ppc4xx_pciex_check_link_sdr()
700 if (!port->has_ibpre || in ppc4xx_pciex_check_link_sdr()
705 port->index); in ppc4xx_pciex_check_link_sdr()
709 "PCIE%d: Link up failed\n", port->index); in ppc4xx_pciex_check_link_sdr()
712 "PCIE%d: link is up !\n", port->index); in ppc4xx_pciex_check_link_sdr()
713 port->link = 1; in ppc4xx_pciex_check_link_sdr()
716 printk(KERN_INFO "PCIE%d: No device detected.\n", port->index); in ppc4xx_pciex_check_link_sdr()
731 * by firmware - let's re-reset RCSSET regs in ppc440spe_pciex_check_reset()
733 * -- Shouldn't we also re-reset the whole thing ? -- BenH in ppc440spe_pciex_check_reset()
750 err = -1; in ppc440spe_pciex_check_reset()
758 err = -1; in ppc440spe_pciex_check_reset()
766 err = -1; in ppc440spe_pciex_check_reset()
774 err = -1; in ppc440spe_pciex_check_reset()
782 err = -1; in ppc440spe_pciex_check_reset()
790 err = -1; in ppc440spe_pciex_check_reset()
806 return -ENXIO; in ppc440spe_pciex_core_init()
812 return -1; in ppc440spe_pciex_core_init()
815 /* De-assert reset of PCIe PLL, wait for lock */ in ppc440spe_pciex_core_init()
821 time_out--; in ppc440spe_pciex_core_init()
828 return -1; in ppc440spe_pciex_core_init()
840 if (port->endpoint) in ppc440spe_pciex_init_port_hw()
845 if (port->index == 0) in ppc440spe_pciex_init_port_hw()
850 mtdcri(SDR0, port->sdr_base + PESDRn_DLPSET, val); in ppc440spe_pciex_init_port_hw()
851 mtdcri(SDR0, port->sdr_base + PESDRn_UTLSET1, 0x20222222); in ppc440spe_pciex_init_port_hw()
853 mtdcri(SDR0, port->sdr_base + PESDRn_UTLSET2, 0x11000000); in ppc440spe_pciex_init_port_hw()
854 mtdcri(SDR0, port->sdr_base + PESDRn_440SPE_HSSL0SET1, 0x35000000); in ppc440spe_pciex_init_port_hw()
855 mtdcri(SDR0, port->sdr_base + PESDRn_440SPE_HSSL1SET1, 0x35000000); in ppc440spe_pciex_init_port_hw()
856 mtdcri(SDR0, port->sdr_base + PESDRn_440SPE_HSSL2SET1, 0x35000000); in ppc440spe_pciex_init_port_hw()
857 mtdcri(SDR0, port->sdr_base + PESDRn_440SPE_HSSL3SET1, 0x35000000); in ppc440spe_pciex_init_port_hw()
858 if (port->index == 0) { in ppc440spe_pciex_init_port_hw()
859 mtdcri(SDR0, port->sdr_base + PESDRn_440SPE_HSSL4SET1, in ppc440spe_pciex_init_port_hw()
861 mtdcri(SDR0, port->sdr_base + PESDRn_440SPE_HSSL5SET1, in ppc440spe_pciex_init_port_hw()
863 mtdcri(SDR0, port->sdr_base + PESDRn_440SPE_HSSL6SET1, in ppc440spe_pciex_init_port_hw()
865 mtdcri(SDR0, port->sdr_base + PESDRn_440SPE_HSSL7SET1, in ppc440spe_pciex_init_port_hw()
868 dcri_clrset(SDR0, port->sdr_base + PESDRn_RCSSET, in ppc440spe_pciex_init_port_hw()
883 port->has_ibpre = 1; in ppc440speB_pciex_init_port_hw()
891 dcr_write(port->dcrs, DCRO_PEGPL_SPECIAL, 0x68782800); in ppc440speA_pciex_init_utl()
896 out_be32(port->utl_base + PEUTL_OUTTR, 0x08000000); in ppc440speA_pciex_init_utl()
897 out_be32(port->utl_base + PEUTL_INTR, 0x02000000); in ppc440speA_pciex_init_utl()
898 out_be32(port->utl_base + PEUTL_OPDBSZ, 0x10000000); in ppc440speA_pciex_init_utl()
899 out_be32(port->utl_base + PEUTL_PBBSZ, 0x53000000); in ppc440speA_pciex_init_utl()
900 out_be32(port->utl_base + PEUTL_IPHBSZ, 0x08000000); in ppc440speA_pciex_init_utl()
901 out_be32(port->utl_base + PEUTL_IPDBSZ, 0x10000000); in ppc440speA_pciex_init_utl()
902 out_be32(port->utl_base + PEUTL_RCIRQEN, 0x00f00000); in ppc440speA_pciex_init_utl()
903 out_be32(port->utl_base + PEUTL_PCTL, 0x80800066); in ppc440speA_pciex_init_utl()
911 out_be32(port->utl_base + PEUTL_PBCTL, 0x08000000); in ppc440speB_pciex_init_utl()
945 if (port->endpoint) in ppc460ex_pciex_init_port_hw()
950 if (port->index == 0) { in ppc460ex_pciex_init_port_hw()
958 mtdcri(SDR0, port->sdr_base + PESDRn_DLPSET, val); in ppc460ex_pciex_init_port_hw()
959 mtdcri(SDR0, port->sdr_base + PESDRn_UTLSET1, utlset1); in ppc460ex_pciex_init_port_hw()
960 mtdcri(SDR0, port->sdr_base + PESDRn_UTLSET2, 0x01210000); in ppc460ex_pciex_init_port_hw()
962 switch (port->index) { in ppc460ex_pciex_init_port_hw()
989 mtdcri(SDR0, port->sdr_base + PESDRn_RCSSET, in ppc460ex_pciex_init_port_hw()
990 mfdcri(SDR0, port->sdr_base + PESDRn_RCSSET) | in ppc460ex_pciex_init_port_hw()
995 switch (port->index) { in ppc460ex_pciex_init_port_hw()
1006 mtdcri(SDR0, port->sdr_base + PESDRn_RCSSET, in ppc460ex_pciex_init_port_hw()
1007 (mfdcri(SDR0, port->sdr_base + PESDRn_RCSSET) & in ppc460ex_pciex_init_port_hw()
1011 port->has_ibpre = 1; in ppc460ex_pciex_init_port_hw()
1018 dcr_write(port->dcrs, DCRO_PEGPL_SPECIAL, 0x0); in ppc460ex_pciex_init_utl()
1023 out_be32(port->utl_base + PEUTL_PBCTL, 0x0800000c); in ppc460ex_pciex_init_utl()
1024 out_be32(port->utl_base + PEUTL_OUTTR, 0x08000000); in ppc460ex_pciex_init_utl()
1025 out_be32(port->utl_base + PEUTL_INTR, 0x02000000); in ppc460ex_pciex_init_utl()
1026 out_be32(port->utl_base + PEUTL_OPDBSZ, 0x04000000); in ppc460ex_pciex_init_utl()
1027 out_be32(port->utl_base + PEUTL_PBBSZ, 0x00000000); in ppc460ex_pciex_init_utl()
1028 out_be32(port->utl_base + PEUTL_IPHBSZ, 0x02000000); in ppc460ex_pciex_init_utl()
1029 out_be32(port->utl_base + PEUTL_IPDBSZ, 0x04000000); in ppc460ex_pciex_init_utl()
1030 out_be32(port->utl_base + PEUTL_RCIRQEN,0x00f00000); in ppc460ex_pciex_init_utl()
1031 out_be32(port->utl_base + PEUTL_PCTL, 0x80800066); in ppc460ex_pciex_init_utl()
1057 * This code is to fix the issue that pci drivers doesn't re-assign in apm821xx_pciex_init_port_hw()
1066 if (port->endpoint) in apm821xx_pciex_init_port_hw()
1073 mtdcri(SDR0, port->sdr_base + PESDRn_DLPSET, val); in apm821xx_pciex_init_port_hw()
1074 mtdcri(SDR0, port->sdr_base + PESDRn_UTLSET1, 0x00000000); in apm821xx_pciex_init_port_hw()
1075 mtdcri(SDR0, port->sdr_base + PESDRn_UTLSET2, 0x01010000); in apm821xx_pciex_init_port_hw()
1085 mtdcri(SDR0, port->sdr_base + PESDRn_RCSSET, in apm821xx_pciex_init_port_hw()
1086 mfdcri(SDR0, port->sdr_base + PESDRn_RCSSET) | in apm821xx_pciex_init_port_hw()
1090 val = PESDR0_460EX_RSTSTA - port->sdr_base; in apm821xx_pciex_init_port_hw()
1093 return -EBUSY; in apm821xx_pciex_init_port_hw()
1095 mtdcri(SDR0, port->sdr_base + PESDRn_RCSSET, in apm821xx_pciex_init_port_hw()
1096 (mfdcri(SDR0, port->sdr_base + PESDRn_RCSSET) & in apm821xx_pciex_init_port_hw()
1100 port->has_ibpre = 1; in apm821xx_pciex_init_port_hw()
1135 /* HSS TX pre-emphasis */ in ppc460sx_pciex_core_init()
1171 /* De-assert PLLRESET */ in ppc460sx_pciex_core_init()
1185 * If bifurcation is not enabled, u-boot would have disabled the in ppc460sx_pciex_core_init()
1202 if (port->endpoint) in ppc460sx_pciex_init_port_hw()
1203 dcri_clrset(SDR0, port->sdr_base + PESDRn_UTLSET2, in ppc460sx_pciex_init_port_hw()
1206 dcri_clrset(SDR0, port->sdr_base + PESDRn_UTLSET2, in ppc460sx_pciex_init_port_hw()
1209 dcri_clrset(SDR0, port->sdr_base + PESDRn_RCSSET, in ppc460sx_pciex_init_port_hw()
1213 port->has_ibpre = 1; in ppc460sx_pciex_init_port_hw()
1220 /* Max 128 Bytes */ in ppc460sx_pciex_init_utl()
1221 out_be32 (port->utl_base + PEUTL_PBBSZ, 0x00000000); in ppc460sx_pciex_init_utl()
1222 /* Assert VRB and TXE - per datasheet turn off addr validation */ in ppc460sx_pciex_init_utl()
1223 out_be32(port->utl_base + PEUTL_PCTL, 0x80800000); in ppc460sx_pciex_init_utl()
1232 port->link = 0; in ppc460sx_pciex_check_link()
1234 mbase = ioremap(port->cfg_space.start + 0x10000000, 0x1000); in ppc460sx_pciex_check_link()
1237 port->node); in ppc460sx_pciex_check_link()
1243 attempt--; in ppc460sx_pciex_check_link()
1247 port->link = 1; in ppc460sx_pciex_check_link()
1271 void __iomem *mbase = ioremap(port->cfg_space.start + 0x10000000, in ppc_476fpe_pciex_check_link()
1274 printk(KERN_INFO "PCIE%d: Checking link...\n", port->index); in ppc_476fpe_pciex_check_link()
1278 port->index); in ppc_476fpe_pciex_check_link()
1282 while (timeout_ms--) { in ppc_476fpe_pciex_check_link()
1291 printk(KERN_INFO "PCIE%d: link is up !\n", port->index); in ppc_476fpe_pciex_check_link()
1292 port->link = 1; in ppc_476fpe_pciex_check_link()
1294 printk(KERN_WARNING "PCIE%d: Link up failed\n", port->index); in ppc_476fpe_pciex_check_link()
1310 int count = -ENODEV; in ppc4xx_pciex_check_core_init()
1316 if (of_device_is_compatible(np, "ibm,plb-pciex-440spe")) { in ppc4xx_pciex_check_core_init()
1322 if (of_device_is_compatible(np, "ibm,plb-pciex-460ex")) in ppc4xx_pciex_check_core_init()
1324 if (of_device_is_compatible(np, "ibm,plb-pciex-460sx")) in ppc4xx_pciex_check_core_init()
1326 if (of_device_is_compatible(np, "ibm,plb-pciex-apm821xx")) in ppc4xx_pciex_check_core_init()
1330 if (of_device_is_compatible(np, "ibm,plb-pciex-476fpe") in ppc4xx_pciex_check_core_init()
1331 || of_device_is_compatible(np, "ibm,plb-pciex-476gtr")) in ppc4xx_pciex_check_core_init()
1336 return -ENODEV; in ppc4xx_pciex_check_core_init()
1339 count = ppc4xx_pciex_hwops->core_init(np); in ppc4xx_pciex_check_core_init()
1349 return -ENOMEM; in ppc4xx_pciex_check_core_init()
1351 return -ENODEV; in ppc4xx_pciex_check_core_init()
1357 dcr_write(port->dcrs, DCRO_PEGPL_CFGBAH, in ppc4xx_pciex_port_init_mapping()
1358 RES_TO_U32_HIGH(port->cfg_space.start)); in ppc4xx_pciex_port_init_mapping()
1359 dcr_write(port->dcrs, DCRO_PEGPL_CFGBAL, in ppc4xx_pciex_port_init_mapping()
1360 RES_TO_U32_LOW(port->cfg_space.start)); in ppc4xx_pciex_port_init_mapping()
1363 dcr_write(port->dcrs, DCRO_PEGPL_CFGMSK, 0xe0000001); in ppc4xx_pciex_port_init_mapping()
1366 dcr_write(port->dcrs, DCRO_PEGPL_REGBAH, in ppc4xx_pciex_port_init_mapping()
1367 RES_TO_U32_HIGH(port->utl_regs.start)); in ppc4xx_pciex_port_init_mapping()
1368 dcr_write(port->dcrs, DCRO_PEGPL_REGBAL, in ppc4xx_pciex_port_init_mapping()
1369 RES_TO_U32_LOW(port->utl_regs.start)); in ppc4xx_pciex_port_init_mapping()
1372 dcr_write(port->dcrs, DCRO_PEGPL_REGMSK, 0x00007001); in ppc4xx_pciex_port_init_mapping()
1374 /* Disable all other outbound windows */ in ppc4xx_pciex_port_init_mapping()
1375 dcr_write(port->dcrs, DCRO_PEGPL_OMR1MSKL, 0); in ppc4xx_pciex_port_init_mapping()
1376 dcr_write(port->dcrs, DCRO_PEGPL_OMR2MSKL, 0); in ppc4xx_pciex_port_init_mapping()
1377 dcr_write(port->dcrs, DCRO_PEGPL_OMR3MSKL, 0); in ppc4xx_pciex_port_init_mapping()
1378 dcr_write(port->dcrs, DCRO_PEGPL_MSGMSK, 0); in ppc4xx_pciex_port_init_mapping()
1386 if (ppc4xx_pciex_hwops->port_init_hw) in ppc4xx_pciex_port_init()
1387 rc = ppc4xx_pciex_hwops->port_init_hw(port); in ppc4xx_pciex_port_init()
1392 * Initialize mapping: disable all regions and configure in ppc4xx_pciex_port_init()
1393 * CFG and REG regions based on resources in the device tree in ppc4xx_pciex_port_init()
1397 if (ppc4xx_pciex_hwops->check_link) in ppc4xx_pciex_port_init()
1398 ppc4xx_pciex_hwops->check_link(port); in ppc4xx_pciex_port_init()
1403 port->utl_base = ioremap(port->utl_regs.start, 0x100); in ppc4xx_pciex_port_init()
1404 BUG_ON(port->utl_base == NULL); in ppc4xx_pciex_port_init()
1407 * Setup UTL registers --BenH. in ppc4xx_pciex_port_init()
1409 if (ppc4xx_pciex_hwops->setup_utl) in ppc4xx_pciex_port_init()
1410 ppc4xx_pciex_hwops->setup_utl(port); in ppc4xx_pciex_port_init()
1415 if (port->sdr_base) { in ppc4xx_pciex_port_init()
1416 if (of_device_is_compatible(port->node, in ppc4xx_pciex_port_init()
1417 "ibm,plb-pciex-460sx")){ in ppc4xx_pciex_port_init()
1418 if (port->link && ppc4xx_pciex_wait_on_sdr(port, in ppc4xx_pciex_port_init()
1422 port->index); in ppc4xx_pciex_port_init()
1423 port->link = 0; in ppc4xx_pciex_port_init()
1425 } else if (port->link && in ppc4xx_pciex_port_init()
1429 port->index); in ppc4xx_pciex_port_init()
1430 port->link = 0; in ppc4xx_pciex_port_init()
1433 dcri_clrset(SDR0, port->sdr_base + PESDRn_RCSSET, 0, 1 << 20); in ppc4xx_pciex_port_init()
1448 if (port->endpoint && bus->number != port->hose->first_busno) in ppc4xx_pciex_validate_bdf()
1452 if (bus->number > port->hose->last_busno) { in ppc4xx_pciex_validate_bdf()
1455 " out of range !\n", bus->number); in ppc4xx_pciex_validate_bdf()
1462 if (bus->number == port->hose->first_busno && devfn != 0) in ppc4xx_pciex_validate_bdf()
1466 if (bus->number == (port->hose->first_busno + 1) && in ppc4xx_pciex_validate_bdf()
1471 if ((bus->number != port->hose->first_busno) && !port->link) in ppc4xx_pciex_validate_bdf()
1486 if (bus->number == port->hose->first_busno) in ppc4xx_pciex_get_config_base()
1487 return (void __iomem *)port->hose->cfg_addr; in ppc4xx_pciex_get_config_base()
1489 relbus = bus->number - (port->hose->first_busno + 1); in ppc4xx_pciex_get_config_base()
1490 return (void __iomem *)port->hose->cfg_data + in ppc4xx_pciex_get_config_base()
1499 &ppc4xx_pciex_ports[hose->indirect_type]; in ppc4xx_pciex_read_config()
1503 BUG_ON(hose != port->hose); in ppc4xx_pciex_read_config()
1511 * Reading from configuration space of non-existing device can in ppc4xx_pciex_read_config()
1515 gpl_cfg = dcr_read(port->dcrs, DCRO_PEGPL_CFG); in ppc4xx_pciex_read_config()
1516 dcr_write(port->dcrs, DCRO_PEGPL_CFG, gpl_cfg | GPL_DMER_MASK_DISA); in ppc4xx_pciex_read_config()
1519 out_be32(port->utl_base + PEUTL_RCSTA, 0x00040000); in ppc4xx_pciex_read_config()
1533 pr_debug("pcie-config-read: bus=%3d [%3d..%3d] devfn=0x%04x" in ppc4xx_pciex_read_config()
1535 bus->number, hose->first_busno, hose->last_busno, in ppc4xx_pciex_read_config()
1539 if (in_be32(port->utl_base + PEUTL_RCSTA) & 0x00040000) { in ppc4xx_pciex_read_config()
1546 dcr_write(port->dcrs, DCRO_PEGPL_CFG, gpl_cfg); in ppc4xx_pciex_read_config()
1556 &ppc4xx_pciex_ports[hose->indirect_type]; in ppc4xx_pciex_write_config()
1566 * Reading from configuration space of non-existing device can in ppc4xx_pciex_write_config()
1570 gpl_cfg = dcr_read(port->dcrs, DCRO_PEGPL_CFG); in ppc4xx_pciex_write_config()
1571 dcr_write(port->dcrs, DCRO_PEGPL_CFG, gpl_cfg | GPL_DMER_MASK_DISA); in ppc4xx_pciex_write_config()
1573 pr_debug("pcie-config-write: bus=%3d [%3d..%3d] devfn=0x%04x" in ppc4xx_pciex_write_config()
1575 bus->number, hose->first_busno, hose->last_busno, in ppc4xx_pciex_write_config()
1590 dcr_write(port->dcrs, DCRO_PEGPL_CFG, gpl_cfg); in ppc4xx_pciex_write_config()
1615 (plb_addr & (size - 1)) != 0) { in ppc4xx_setup_one_pciex_POM()
1616 printk(KERN_WARNING "%pOF: Resource out of range\n", hose->dn); in ppc4xx_setup_one_pciex_POM()
1617 return -1; in ppc4xx_setup_one_pciex_POM()
1632 dcr_write(port->dcrs, DCRO_PEGPL_OMR1BAH, lah); in ppc4xx_setup_one_pciex_POM()
1633 dcr_write(port->dcrs, DCRO_PEGPL_OMR1BAL, lal); in ppc4xx_setup_one_pciex_POM()
1634 dcr_write(port->dcrs, DCRO_PEGPL_OMR1MSKH, 0x7fffffff); in ppc4xx_setup_one_pciex_POM()
1636 if (of_device_is_compatible(port->node, "ibm,plb-pciex-460sx")) in ppc4xx_setup_one_pciex_POM()
1637 dcr_write(port->dcrs, DCRO_PEGPL_OMR1MSKL, in ppc4xx_setup_one_pciex_POM()
1641 port->node, "ibm,plb-pciex-476fpe") || in ppc4xx_setup_one_pciex_POM()
1643 port->node, "ibm,plb-pciex-476gtr")) in ppc4xx_setup_one_pciex_POM()
1644 dcr_write(port->dcrs, DCRO_PEGPL_OMR1MSKL, in ppc4xx_setup_one_pciex_POM()
1648 dcr_write(port->dcrs, DCRO_PEGPL_OMR1MSKL, in ppc4xx_setup_one_pciex_POM()
1655 dcr_write(port->dcrs, DCRO_PEGPL_OMR2BAH, lah); in ppc4xx_setup_one_pciex_POM()
1656 dcr_write(port->dcrs, DCRO_PEGPL_OMR2BAL, lal); in ppc4xx_setup_one_pciex_POM()
1657 dcr_write(port->dcrs, DCRO_PEGPL_OMR2MSKH, 0x7fffffff); in ppc4xx_setup_one_pciex_POM()
1658 dcr_write(port->dcrs, DCRO_PEGPL_OMR2MSKL, in ppc4xx_setup_one_pciex_POM()
1664 dcr_write(port->dcrs, DCRO_PEGPL_OMR3BAH, lah); in ppc4xx_setup_one_pciex_POM()
1665 dcr_write(port->dcrs, DCRO_PEGPL_OMR3BAL, lal); in ppc4xx_setup_one_pciex_POM()
1666 dcr_write(port->dcrs, DCRO_PEGPL_OMR3MSKH, 0x7fffffff); in ppc4xx_setup_one_pciex_POM()
1668 dcr_write(port->dcrs, DCRO_PEGPL_OMR3MSKL, in ppc4xx_setup_one_pciex_POM()
1683 /* Setup outbound memory windows */ in ppc4xx_configure_pciex_POMs()
1685 struct resource *res = &hose->mem_resources[i]; in ppc4xx_configure_pciex_POMs()
1686 resource_size_t offset = hose->mem_offset[i]; in ppc4xx_configure_pciex_POMs()
1689 if (!(res->flags & IORESOURCE_MEM)) in ppc4xx_configure_pciex_POMs()
1693 port->node); in ppc4xx_configure_pciex_POMs()
1699 res->start, in ppc4xx_configure_pciex_POMs()
1700 res->start - offset, in ppc4xx_configure_pciex_POMs()
1702 res->flags, in ppc4xx_configure_pciex_POMs()
1709 if (res->start == offset) in ppc4xx_configure_pciex_POMs()
1715 if (j <= 1 && !found_isa_hole && hose->isa_mem_size) in ppc4xx_configure_pciex_POMs()
1717 hose->isa_mem_phys, 0, in ppc4xx_configure_pciex_POMs()
1718 hose->isa_mem_size, 0, j) == 0) in ppc4xx_configure_pciex_POMs()
1720 hose->dn); in ppc4xx_configure_pciex_POMs()
1723 * Note also that it -has- to be region index 2 on this HW in ppc4xx_configure_pciex_POMs()
1725 if (hose->io_resource.flags & IORESOURCE_IO) in ppc4xx_configure_pciex_POMs()
1727 hose->io_base_phys, 0, in ppc4xx_configure_pciex_POMs()
1739 if (port->endpoint) { in ppc4xx_configure_pciex_PIMs()
1769 if (res->flags & IORESOURCE_PREFETCH) in ppc4xx_configure_pciex_PIMs()
1772 if (of_device_is_compatible(port->node, "ibm,plb-pciex-460sx") || in ppc4xx_configure_pciex_PIMs()
1774 port->node, "ibm,plb-pciex-476fpe") || in ppc4xx_configure_pciex_PIMs()
1776 port->node, "ibm,plb-pciex-476gtr")) in ppc4xx_configure_pciex_PIMs()
1792 out_le32(mbase + PCI_BASE_ADDRESS_0, RES_TO_U32_LOW(res->start)); in ppc4xx_configure_pciex_PIMs()
1793 out_le32(mbase + PCI_BASE_ADDRESS_1, RES_TO_U32_HIGH(res->start)); in ppc4xx_configure_pciex_PIMs()
1816 primary = of_property_read_bool(port->node, "primary"); in ppc4xx_pciex_port_setup_hose()
1819 bus_range = of_get_property(port->node, "bus-range", NULL); in ppc4xx_pciex_port_setup_hose()
1822 hose = pcibios_alloc_controller(port->node); in ppc4xx_pciex_port_setup_hose()
1829 hose->indirect_type = port->index; in ppc4xx_pciex_port_setup_hose()
1832 hose->first_busno = bus_range ? bus_range[0] : 0x0; in ppc4xx_pciex_port_setup_hose()
1833 hose->last_busno = bus_range ? bus_range[1] : 0xff; in ppc4xx_pciex_port_setup_hose()
1840 busses = hose->last_busno - hose->first_busno; /* This is off by 1 */ in ppc4xx_pciex_port_setup_hose()
1843 hose->last_busno = hose->first_busno + busses; in ppc4xx_pciex_port_setup_hose()
1846 if (!port->endpoint) { in ppc4xx_pciex_port_setup_hose()
1848 * PCIe root-complexes. External space is 1M per bus in ppc4xx_pciex_port_setup_hose()
1850 cfg_data = ioremap(port->cfg_space.start + in ppc4xx_pciex_port_setup_hose()
1851 (hose->first_busno + 1) * 0x100000, in ppc4xx_pciex_port_setup_hose()
1855 port->node); in ppc4xx_pciex_port_setup_hose()
1858 hose->cfg_data = cfg_data; in ppc4xx_pciex_port_setup_hose()
1864 mbase = ioremap(port->cfg_space.start + 0x10000000, 0x1000); in ppc4xx_pciex_port_setup_hose()
1867 port->node); in ppc4xx_pciex_port_setup_hose()
1870 hose->cfg_addr = mbase; in ppc4xx_pciex_port_setup_hose()
1872 pr_debug("PCIE %pOF, bus %d..%d\n", port->node, in ppc4xx_pciex_port_setup_hose()
1873 hose->first_busno, hose->last_busno); in ppc4xx_pciex_port_setup_hose()
1875 hose->cfg_addr, hose->cfg_data); in ppc4xx_pciex_port_setup_hose()
1878 hose->ops = &ppc4xx_pciex_pci_ops; in ppc4xx_pciex_port_setup_hose()
1879 port->hose = hose; in ppc4xx_pciex_port_setup_hose()
1880 mbase = (void __iomem *)hose->cfg_addr; in ppc4xx_pciex_port_setup_hose()
1882 if (!port->endpoint) { in ppc4xx_pciex_port_setup_hose()
1886 out_8(mbase + PCI_PRIMARY_BUS, hose->first_busno); in ppc4xx_pciex_port_setup_hose()
1887 out_8(mbase + PCI_SECONDARY_BUS, hose->first_busno + 1); in ppc4xx_pciex_port_setup_hose()
1888 out_8(mbase + PCI_SUBORDINATE_BUS, hose->last_busno); in ppc4xx_pciex_port_setup_hose()
1896 /* Parse outbound mapping resources */ in ppc4xx_pciex_port_setup_hose()
1897 pci_process_bridge_OF_ranges(hose, port->node, primary); in ppc4xx_pciex_port_setup_hose()
1903 /* Configure outbound ranges POMs */ in ppc4xx_pciex_port_setup_hose()
1912 * overwritten by setting the "vendor-id/device-id" properties in ppc4xx_pciex_port_setup_hose()
1916 /* Get the (optional) vendor-/device-id from the device-tree */ in ppc4xx_pciex_port_setup_hose()
1917 pval = of_get_property(port->node, "vendor-id", NULL); in ppc4xx_pciex_port_setup_hose()
1921 if (!port->endpoint) in ppc4xx_pciex_port_setup_hose()
1922 val = 0xaaa0 + port->index; in ppc4xx_pciex_port_setup_hose()
1924 val = 0xeee0 + port->index; in ppc4xx_pciex_port_setup_hose()
1928 pval = of_get_property(port->node, "device-id", NULL); in ppc4xx_pciex_port_setup_hose()
1932 if (!port->endpoint) in ppc4xx_pciex_port_setup_hose()
1933 val = 0xbed0 + port->index; in ppc4xx_pciex_port_setup_hose()
1935 val = 0xfed0 + port->index; in ppc4xx_pciex_port_setup_hose()
1940 if (of_device_is_compatible(port->node, "ibm,plb-pciex-460sx")) in ppc4xx_pciex_port_setup_hose()
1943 if (!port->endpoint) { in ppc4xx_pciex_port_setup_hose()
1944 /* Set Class Code to PCI-PCI bridge and Revision Id to 1 */ in ppc4xx_pciex_port_setup_hose()
1947 printk(KERN_INFO "PCIE%d: successfully set as root-complex\n", in ppc4xx_pciex_port_setup_hose()
1948 port->index); in ppc4xx_pciex_port_setup_hose()
1954 port->index); in ppc4xx_pciex_port_setup_hose()
1980 /* Get the port number from the device-tree */ in ppc4xx_probe_pciex_bridge()
1993 port->index = portno; in ppc4xx_probe_pciex_bridge()
1999 printk(KERN_INFO "PCIE%d: Port disabled via device-tree\n", port->index); in ppc4xx_probe_pciex_bridge()
2003 port->node = of_node_get(np); in ppc4xx_probe_pciex_bridge()
2004 if (ppc4xx_pciex_hwops->want_sdr) { in ppc4xx_probe_pciex_bridge()
2005 pval = of_get_property(np, "sdr-base", NULL); in ppc4xx_probe_pciex_bridge()
2007 printk(KERN_ERR "PCIE: missing sdr-base for %pOF\n", in ppc4xx_probe_pciex_bridge()
2011 port->sdr_base = *pval; in ppc4xx_probe_pciex_bridge()
2014 /* Check if device_type property is set to "pci" or "pci-endpoint". in ppc4xx_probe_pciex_bridge()
2016 * as root-complex or as endpoint. in ppc4xx_probe_pciex_bridge()
2018 if (of_node_is_type(port->node, "pci-endpoint")) { in ppc4xx_probe_pciex_bridge()
2019 port->endpoint = 1; in ppc4xx_probe_pciex_bridge()
2020 } else if (of_node_is_type(port->node, "pci")) { in ppc4xx_probe_pciex_bridge()
2021 port->endpoint = 0; in ppc4xx_probe_pciex_bridge()
2029 if (of_address_to_resource(np, 0, &port->cfg_space)) { in ppc4xx_probe_pciex_bridge()
2030 printk(KERN_ERR "%pOF: Can't get PCI-E config space !", np); in ppc4xx_probe_pciex_bridge()
2034 if (of_address_to_resource(np, 1, &port->utl_regs)) { in ppc4xx_probe_pciex_bridge()
2045 port->dcrs = dcr_map(np, dcrs, dcr_resource_len(np, 0)); in ppc4xx_probe_pciex_bridge()
2049 printk(KERN_WARNING "PCIE%d: Port init failed\n", port->index); in ppc4xx_probe_pciex_bridge()
2066 for_each_compatible_node(np, NULL, "ibm,plb-pciex") in ppc4xx_pci_find_bridges()
2069 for_each_compatible_node(np, NULL, "ibm,plb-pcix") in ppc4xx_pci_find_bridges()
2071 for_each_compatible_node(np, NULL, "ibm,plb-pci") in ppc4xx_pci_find_bridges()