1 // SPDX-License-Identifier: GPL-2.0-or-later
12  * code to detect this card though and disable SMP. --BenH.
18  * Copyright (C) XLR8, Inc. 1994-2000
38 #include <asm/text-patching.h>
66 static void (*pmac_tb_freeze)(int freeze);
86 /* N.B. this is the PCI config space address register for the 1st bridge */
89 /* Daystar/XLR8 4-CPU card */
115 #define PSURGE_NONE		-1
162  *  -- paulus.
191 	int rc = -ENOMEM;  in psurge_secondary_ipi_init()
224 	/* bogus is not necessarily cacheline-aligned,  in psurge_quad_probe()
225 	   though I don't suppose that really matters.  -- paulus */  in psurge_quad_probe()
281 	 * in the hammerhead memory controller in the case of the  in smp_psurge_probe()
282 	 * dual-cpu powersurge board.  -- paulus.  in smp_psurge_probe()
299 		smp_ops->give_timebase = smp_generic_give_timebase;  in smp_psurge_probe()
300 		smp_ops->take_timebase = smp_generic_take_timebase;  in smp_psurge_probe()
304 			/* not a dual-cpu card */  in smp_psurge_probe()
328 	if (ppc_md.progress) ppc_md.progress("smp_psurge_probe - done", 0x352);  in smp_psurge_probe()
350 	/* This is going to freeze the timeebase, we disable interrupts */  in smp_psurge_kick_cpu()
367 	 * caller which will try to do udelay's etc... Instead, we wait -here-  in smp_psurge_kick_cpu()
395 	if (ppc_md.progress) ppc_md.progress("smp_psurge_kick_cpu - done", 0x354);  in smp_psurge_kick_cpu()
437 /* PowerSurge-style Macs */
498  * G5s enable/disable the timebase via an i2c-connected clock chip.
503 static void smp_core99_cypress_tb_freeze(int freeze)  in smp_core99_cypress_tb_freeze()  argument
508 	/* Strangely, the device-tree says address is 0xd2, but darwin  in smp_core99_cypress_tb_freeze()
519 	data = (data & 0xf3) | (freeze ? 0x00 : 0x0c);  in smp_core99_cypress_tb_freeze()
529 		       freeze ? "freeze" : "unfreeze", rc);  in smp_core99_cypress_tb_freeze()
530 		panic("Timebase freeze failed !\n");  in smp_core99_cypress_tb_freeze()
535 static void smp_core99_pulsar_tb_freeze(int freeze)  in smp_core99_pulsar_tb_freeze()  argument
548 	data = (data & 0x88) | (freeze ? 0x11 : 0x22);  in smp_core99_pulsar_tb_freeze()
557 		       freeze ? "freeze" : "unfreeze", rc);  in smp_core99_pulsar_tb_freeze()
558 		panic("Timebase freeze failed !\n");  in smp_core99_pulsar_tb_freeze()
571 	for_each_node_by_name(cc, "i2c-hwclock") {  in smp_core99_setup_i2c_hwsync()
573 		ok = p && of_device_is_compatible(p, "uni-n-i2c");  in smp_core99_setup_i2c_hwsync()
586 			if (of_device_is_compatible(cc,"pulsar-legacy-slewing")) {  in smp_core99_setup_i2c_hwsync()
628 static void smp_core99_pfunc_tb_freeze(int freeze)  in smp_core99_pfunc_tb_freeze()  argument
636 	args.u[0].v = !freeze;  in smp_core99_pfunc_tb_freeze()
637 	pmf_call_function(cpus, "cpu-timebase", &args);  in smp_core99_pfunc_tb_freeze()
647 static unsigned int core99_tb_gpio;	/* Timebase freeze GPIO */
649 static void smp_core99_gpio_tb_freeze(int freeze)  in smp_core99_gpio_tb_freeze()  argument
651 	if (freeze)  in smp_core99_gpio_tb_freeze()
711 		    of_property_read_bool(cpus, "platform-cpu-timebase")) {  in smp_core99_setup()
729 			tbprop = of_get_property(cpu, "timebase-enable", NULL);  in smp_core99_setup()
743 		smp_ops->give_timebase = smp_generic_give_timebase;  in smp_core99_setup()
744 		smp_ops->take_timebase = smp_generic_take_timebase;  in smp_core99_setup()
770 	/* Count CPUs in the device-tree */  in smp_core99_probe()
803 		return -ENOENT;  in smp_core99_kick_cpu()
825 	 * in a RAM-based wait loop like CHRP.  in smp_core99_kick_cpu()
956 	 * Re-enable interrupts. The NAP code needs to enable them  in pmac_cpu_offline_self()
958 	 * happened while soft-disabled.  in pmac_cpu_offline_self()
998 	np = of_find_node_by_name(NULL, "uni-n");  in pmac_setup_smp()
1023 	smp_ops->cpu_offline_self = pmac_cpu_offline_self;  in pmac_setup_smp()