35 		.mask	= IPIC_SIMSR_H,
42 		.mask	= IPIC_SIMSR_H,
49 		.mask	= IPIC_SIMSR_H,
56 		.mask	= IPIC_SIMSR_H,
63 		.mask	= IPIC_SIMSR_H,
70 		.mask	= IPIC_SIMSR_H,
77 		.mask	= IPIC_SIMSR_H,
84 		.mask	= IPIC_SIMSR_H,
91 		.mask	= IPIC_SIMSR_H,
98 		.mask	= IPIC_SIMSR_H,
105 		.mask	= IPIC_SIMSR_H,
112 		.mask	= IPIC_SIMSR_H,
119 		.mask	= IPIC_SIMSR_H,
126 		.mask	= IPIC_SIMSR_H,
133 		.mask	= IPIC_SIMSR_H,
140 		.mask	= IPIC_SIMSR_H,
148 		.mask	= IPIC_SEMSR,
156 		.mask	= IPIC_SEMSR,
164 		.mask	= IPIC_SEMSR,
172 		.mask	= IPIC_SEMSR,
180 		.mask	= IPIC_SEMSR,
188 		.mask	= IPIC_SEMSR,
196 		.mask	= IPIC_SEMSR,
203 		.mask	= IPIC_SIMSR_H,
210 		.mask	= IPIC_SIMSR_H,
217 		.mask	= IPIC_SIMSR_H,
224 		.mask	= IPIC_SIMSR_H,
231 		.mask	= IPIC_SIMSR_H,
238 		.mask	= IPIC_SIMSR_H,
245 		.mask	= IPIC_SIMSR_H,
252 		.mask	= IPIC_SIMSR_H,
259 		.mask	= IPIC_SIMSR_H,
266 		.mask	= IPIC_SIMSR_H,
273 		.mask	= IPIC_SIMSR_H,
280 		.mask	= IPIC_SIMSR_H,
287 		.mask	= IPIC_SIMSR_H,
294 		.mask	= IPIC_SIMSR_H,
301 		.mask	= IPIC_SIMSR_H,
308 		.mask	= IPIC_SIMSR_H,
316 		.mask	= IPIC_SEMSR,
323 		.mask	= IPIC_SIMSR_L,
330 		.mask	= IPIC_SIMSR_L,
337 		.mask	= IPIC_SIMSR_L,
344 		.mask	= IPIC_SIMSR_L,
351 		.mask	= IPIC_SIMSR_L,
358 		.mask	= IPIC_SIMSR_L,
365 		.mask	= IPIC_SIMSR_L,
372 		.mask	= IPIC_SIMSR_L,
379 		.mask	= IPIC_SIMSR_L,
385 		.mask	= IPIC_SIMSR_L,
391 		.mask	= IPIC_SIMSR_L,
397 		.mask	= IPIC_SIMSR_L,
403 		.mask	= IPIC_SIMSR_L,
409 		.mask	= IPIC_SIMSR_L,
415 		.mask	= IPIC_SIMSR_L,
421 		.mask	= IPIC_SIMSR_L,
427 		.mask	= IPIC_SIMSR_L,
433 		.mask	= IPIC_SIMSR_L,
439 		.mask	= IPIC_SIMSR_L,
445 		.mask	= IPIC_SIMSR_L,
451 		.mask	= IPIC_SIMSR_L,
457 		.mask	= IPIC_SIMSR_L,
463 		.mask	= IPIC_SIMSR_L,
469 		.mask	= IPIC_SIMSR_L,
475 		.mask	= IPIC_SIMSR_L,
481 		.mask	= IPIC_SIMSR_L,
487 		.mask	= IPIC_SIMSR_L,
493 		.mask	= IPIC_SIMSR_L,
499 		.mask	= IPIC_SIMSR_L,
530 	temp = ipic_read(ipic->regs, ipic_info[src].mask);  in ipic_unmask_irq()
532 	ipic_write(ipic->regs, ipic_info[src].mask, temp);  in ipic_unmask_irq()
546 	temp = ipic_read(ipic->regs, ipic_info[src].mask);  in ipic_mask_irq()
548 	ipic_write(ipic->regs, ipic_info[src].mask, temp);  in ipic_mask_irq()
585 	temp = ipic_read(ipic->regs, ipic_info[src].mask);  in ipic_mask_irq_and_ack()
587 	ipic_write(ipic->regs, ipic_info[src].mask, temp);  in ipic_mask_irq_and_ack()
786 void ipic_clear_mcp_status(u32 mask)  in ipic_clear_mcp_status()  argument
788 	ipic_write(primary_ipic->regs, IPIC_SERSR, mask);  in ipic_clear_mcp_status()