Lines Matching +full:per +full:- +full:hart
1 /* SPDX-License-Identifier: GPL-2.0-only */
16 #include <asm/asm-offsets.h>
60 * bit_pos = cpu % 64 = cpu - (cpu / 64) * 64 = cpu - (cpu >> 6) << 6
61 * = cpu - ((cpu >> 6) << 3) << 3
109 * The RISC-V kernel does not eagerly emit a sfence.vma after each
111 * - if the uarch caches invalid entries, the new mapping would not be
113 * - if the uarch does not cache invalid entries, a reordered access
123 addi sp, sp, -(PT_SIZE_ON_STACK)
133 addi sp, sp, -(PT_SIZE_ON_STACK)
140 * Disable user-mode memory access as it should only be set in the
209 * - handle_exception
210 * - ret_from_fork
248 * different hart contexts. We can't actually save and restore a load
249 * reservation, so instead here we clear any existing reservation --
256 * forward branch around an SC -- which is how we implement CAS. As a
296 addi sp, sp, -(PT_SIZE_ON_STACK)
339 * Calls func(regs) using the per-CPU IRQ stack.
343 addi sp, sp, -STACKFRAME_SIZE_ON_STACK
348 /* Switch to the per-CPU shadow call stack */
352 /* Switch to the per-CPU IRQ stack and call the handler */
362 addi sp, s0, -STACKFRAME_SIZE_ON_STACK
373 * The callee-saved registers must be saved and restored.
382 /* Save context into prev->thread */
402 /* Restore context from next->thread */