1 // SPDX-License-Identifier: GPL-2.0+
7 #include "decode-insn.h"
8 #include "simulate-insn.h"
39 	 *     31    30       21    20     19        12 11 7 6      0  in simulate_jal()
40 	 * imm [20] | imm[10:1] | imm[11] | imm[19:12] | rd | opcode  in simulate_jal()
45 	u32 index = (opcode >> 7) & 0x1f;  in simulate_jal()
52 	imm |= ((opcode >> 20) & 0x1)   << 11;  in simulate_jal()
64 	 * 31          20 19 15 14 12 11 7 6      0  in simulate_jalr()
65 	 *  offset[11:0] | rs1 | 010 | rd | opcode  in simulate_jalr()
71 	u32 rd_index = (opcode >> 7) & 0x1f;  in simulate_jalr()
82 	instruction_pointer_set(regs, (base_addr + sign_extend32((imm), 11))&~1);  in simulate_jalr()
88 	((opcode >> 7) & 0x1f)
105 	 *  31        12 11 7 6      0  in simulate_auipc()
107 	 *        20       5     7  in simulate_auipc()
133 	 ((((opcode) >>  7) & 0x1 ) << 11) | \
143 	 *      31    30       25 24 20 19 15 14    12 11       8    7      6      0  in simulate_branch()
144 	 * | imm[12] | imm[10:5] | rs2 | rs1 | funct3 | imm[4:1] | imm[11] | opcode |  in simulate_branch()
145 	 *     1           6        5     5      3         4         1         7  in simulate_branch()
146 	 *     imm[12|10:5]        rs2   rs1    000       imm[4:1|11]       1100011  BEQ  in simulate_branch()
147 	 *     imm[12|10:5]        rs2   rs1    001       imm[4:1|11]       1100011  BNE  in simulate_branch()
148 	 *     imm[12|10:5]        rs2   rs1    100       imm[4:1|11]       1100011  BLT  in simulate_branch()
149 	 *     imm[12|10:5]        rs2   rs1    101       imm[4:1|11]       1100011  BGE  in simulate_branch()
150 	 *     imm[12|10:5]        rs2   rs1    110       imm[4:1|11]       1100011  BLTU  in simulate_branch()
151 	 *     imm[12|10:5]        rs2   rs1    111       imm[4:1|11]       1100011  BGEU  in simulate_branch()
196 	 * | funct3 | offset[11|4|9:8|10|6|7|3:1|5] | opcode |  in simulate_c_j()
197 	 *     3                   11                    2  in simulate_c_j()
203 	offset |= ((opcode >> 11) & 0x1) << 4;  in simulate_c_j()
205 	offset |= ((opcode >> 7)  & 0x1) << 6;  in simulate_c_j()
206 	offset |= ((opcode >> 6)  & 0x1) << 7;  in simulate_c_j()
209 	offset |= ((opcode >> 12) & 0x1) << 11;  in simulate_c_j()
211 	instruction_pointer_set(regs, addr + sign_extend32(offset, 11));  in simulate_c_j()
220 	 *  15    12 11  7 6   2 1  0  in simulate_c_jr_jalr()
227 	u32 rs1 = (opcode >> 7) & 0x1f;  in simulate_c_jr_jalr()
257 	 *  15    13 12           10 9    7 6                 2 1  0  in simulate_c_bnez_beqz()
258 	 * | funct3 | offset[8|4:3] | rs1' | offset[7:6|2:1|5] | op |  in simulate_c_bnez_beqz()
266 	rs1 = 0x8 | ((opcode >> 7) & 0x7);  in simulate_c_bnez_beqz()