Lines Matching +full:ia32 +full:- +full:3 +full:a
1 /* SPDX-License-Identifier: GPL-2.0 */
6 #include <asm/required-features.h>
10 #include <asm/disabled-features.h>
16 #define NCAPINTS 22 /* N 32-bit words worth of info */
17 #define NBUGINTS 2 /* N 32-bit bug flags */
20 * Note: If the comment begins with a quoted string, that string is used
25 * please update the table in kernel/cpu/cpuid-deps.c as well.
28 /* Intel-defined CPU features, CPUID level 0x00000001 (EDX), word 0 */
32 #define X86_FEATURE_PSE ( 0*32+ 3) /* "pse" Page Size Extensions */
34 #define X86_FEATURE_MSR ( 0*32+ 5) /* "msr" Model-Specific Registers */
45 #define X86_FEATURE_PSE36 ( 0*32+17) /* "pse36" 36-bit PSEs */
55 #define X86_FEATURE_HT ( 0*32+28) /* "ht" Hyper-Threading */
57 #define X86_FEATURE_IA64 ( 0*32+30) /* "ia64" IA-64 processor */
60 /* AMD-defined CPU features, CPUID level 0x80000001, word 1 */
69 #define X86_FEATURE_LM ( 1*32+29) /* "lm" Long Mode (x86-64, 64-bit support) */
70 #define X86_FEATURE_3DNOWEXT ( 1*32+30) /* "3dnowext" AMD 3DNow extensions */
71 #define X86_FEATURE_3DNOW ( 1*32+31) /* "3dnow" 3DNow */
73 /* Transmeta-defined CPU features, CPUID level 0x80860001, word 2 */
76 #define X86_FEATURE_LRTI ( 2*32+ 3) /* "lrti" LongRun table interface */
78 /* Other features, Linux-defined mapping, word 3 */
80 #define X86_FEATURE_CXMMX ( 3*32+ 0) /* "cxmmx" Cyrix MMX extensions */
81 #define X86_FEATURE_K6_MTRR ( 3*32+ 1) /* "k6_mtrr" AMD K6 nonstandard MTRRs */
82 #define X86_FEATURE_CYRIX_ARR ( 3*32+ 2) /* "cyrix_arr" Cyrix ARRs (= MTRRs) */
83 #define X86_FEATURE_CENTAUR_MCR ( 3*32+ 3) /* "centaur_mcr" Centaur MCRs (= MTRRs) */
84 #define X86_FEATURE_K8 ( 3*32+ 4) /* Opteron, Athlon64 */
85 #define X86_FEATURE_ZEN5 ( 3*32+ 5) /* CPU based on Zen5 microarchitecture */
86 /* Free ( 3*32+ 6) */
87 /* Free ( 3*32+ 7) */
88 #define X86_FEATURE_CONSTANT_TSC ( 3*32+ 8) /* "constant_tsc" TSC ticks at a constant rate */
89 #define X86_FEATURE_UP ( 3*32+ 9) /* "up" SMP kernel running on UP */
90 #define X86_FEATURE_ART ( 3*32+10) /* "art" Always running timer (ART) */
91 #define X86_FEATURE_ARCH_PERFMON ( 3*32+11) /* "arch_perfmon" Intel Architectural PerfMon */
92 #define X86_FEATURE_PEBS ( 3*32+12) /* "pebs" Precise-Event Based Sampling */
93 #define X86_FEATURE_BTS ( 3*32+13) /* "bts" Branch Trace Store */
94 #define X86_FEATURE_SYSCALL32 ( 3*32+14) /* syscall in IA32 userspace */
95 #define X86_FEATURE_SYSENTER32 ( 3*32+15) /* sysenter in IA32 userspace */
96 #define X86_FEATURE_REP_GOOD ( 3*32+16) /* "rep_good" REP microcode works well */
97 #define X86_FEATURE_AMD_LBR_V2 ( 3*32+17) /* "amd_lbr_v2" AMD Last Branch Record Extension Version…
98 #define X86_FEATURE_CLEAR_CPU_BUF ( 3*32+18) /* Clear CPU buffers using VERW */
99 #define X86_FEATURE_ACC_POWER ( 3*32+19) /* "acc_power" AMD Accumulated Power Mechanism */
100 #define X86_FEATURE_NOPL ( 3*32+20) /* "nopl" The NOPL (0F 1F) instructions */
101 #define X86_FEATURE_ALWAYS ( 3*32+21) /* Always-present feature */
102 #define X86_FEATURE_XTOPOLOGY ( 3*32+22) /* "xtopology" CPU topology enum extensions */
103 #define X86_FEATURE_TSC_RELIABLE ( 3*32+23) /* "tsc_reliable" TSC is known to be reliable */
104 #define X86_FEATURE_NONSTOP_TSC ( 3*32+24) /* "nonstop_tsc" TSC does not stop in C states */
105 #define X86_FEATURE_CPUID ( 3*32+25) /* "cpuid" CPU has CPUID instruction itself */
106 #define X86_FEATURE_EXTD_APICID ( 3*32+26) /* "extd_apicid" Extended APICID (8 bits) */
107 #define X86_FEATURE_AMD_DCM ( 3*32+27) /* "amd_dcm" AMD multi-node processor */
108 #define X86_FEATURE_APERFMPERF ( 3*32+28) /* "aperfmperf" P-State hardware coordination feedback c…
109 #define X86_FEATURE_RAPL ( 3*32+29) /* "rapl" AMD/Hygon RAPL interface */
110 #define X86_FEATURE_NONSTOP_TSC_S3 ( 3*32+30) /* "nonstop_tsc_s3" TSC doesn't stop in S3 state */
111 #define X86_FEATURE_TSC_KNOWN_FREQ ( 3*32+31) /* "tsc_known_freq" TSC has known frequency */
113 /* Intel-defined CPU features, CPUID level 0x00000001 (ECX), word 4 */
114 #define X86_FEATURE_XMM3 ( 4*32+ 0) /* "pni" SSE-3 */
116 #define X86_FEATURE_DTES64 ( 4*32+ 2) /* "dtes64" 64-bit Debug Store */
117 #define X86_FEATURE_MWAIT ( 4*32+ 3) /* "monitor" MONITOR/MWAIT support */
118 #define X86_FEATURE_DSCPL ( 4*32+ 4) /* "ds_cpl" CPL-qualified (filtered) Debug Store */
123 #define X86_FEATURE_SSSE3 ( 4*32+ 9) /* "ssse3" Supplemental SSE-3 */
126 #define X86_FEATURE_FMA ( 4*32+12) /* "fma" Fused multiply-add */
132 #define X86_FEATURE_XMM4_1 ( 4*32+19) /* "sse4_1" SSE-4.1 */
133 #define X86_FEATURE_XMM4_2 ( 4*32+20) /* "sse4_2" SSE-4.2 */
142 #define X86_FEATURE_F16C ( 4*32+29) /* "f16c" 16-bit FP conversions */
144 #define X86_FEATURE_HYPERVISOR ( 4*32+31) /* "hypervisor" Running on a hypervisor */
146 /* VIA/Cyrix/Centaur-defined CPU features, CPUID level 0xC0000001, word 5 */
148 #define X86_FEATURE_XSTORE_EN ( 5*32+ 3) /* "rng_en" RNG enabled */
149 #define X86_FEATURE_XCRYPT ( 5*32+ 6) /* "ace" on-CPU crypto (xcrypt) */
150 #define X86_FEATURE_XCRYPT_EN ( 5*32+ 7) /* "ace_en" on-CPU crypto enabled */
162 #define X86_FEATURE_EXTAPIC ( 6*32+ 3) /* "extapic" Extended APIC space */
163 #define X86_FEATURE_CR8_LEGACY ( 6*32+ 4) /* "cr8_legacy" CR8 in 32-bit mode */
165 #define X86_FEATURE_SSE4A ( 6*32+ 6) /* "sse4a" SSE-4A */
167 #define X86_FEATURE_3DNOWPREFETCH ( 6*32+ 8) /* "3dnowprefetch" 3DNow prefetch instructions */
182 #define X86_FEATURE_PTSC ( 6*32+27) /* "ptsc" Performance time-stamp counter */
187 * Auxiliary flags: Linux defined - For features scattered in various
192 #define X86_FEATURE_RING3MWAIT ( 7*32+ 0) /* "ring3mwait" Ring 3 MONITOR/MWAIT instructions */
195 #define X86_FEATURE_EPB ( 7*32+ 3) /* "epb" IA32_ENERGY_PERF_BIAS support */
199 #define X86_FEATURE_TDX_HOST_PLATFORM ( 7*32+ 7) /* "tdx_host_platform" Platform supports being a T…
200 #define X86_FEATURE_HW_PSTATE ( 7*32+ 8) /* "hw_pstate" AMD HW-PState */
205 #define X86_FEATURE_RSB_VMEXIT ( 7*32+13) /* Fill RSB on VM-Exit */
218 #define X86_FEATURE_IBPB ( 7*32+26) /* "ibpb" Indirect Branch Prediction Barrier without a guarant…
229 #define X86_FEATURE_VPID ( 8*32+ 3) /* "vpid" Intel Virtual Processor ID */
233 #define X86_FEATURE_EPT_AD ( 8*32+17) /* "ept_ad" Intel Extended Page Table access-dirty bit */
240 /* Intel-defined CPU features, CPUID level 0x00000007:0 (EBX), word 9 */
244 #define X86_FEATURE_BMI1 ( 9*32+ 3) /* "bmi1" 1st group bit manipulation extensions */
257 #define X86_FEATURE_AVX512F ( 9*32+16) /* "avx512f" AVX-512 Foundation */
258 #define X86_FEATURE_AVX512DQ ( 9*32+17) /* "avx512dq" AVX-512 DQ (Double/Quad granular) Instructio…
262 #define X86_FEATURE_AVX512IFMA ( 9*32+21) /* "avx512ifma" AVX-512 Integer Fused Multiply-Add instr…
266 #define X86_FEATURE_AVX512PF ( 9*32+26) /* "avx512pf" AVX-512 Prefetch */
267 #define X86_FEATURE_AVX512ER ( 9*32+27) /* "avx512er" AVX-512 Exponential and Reciprocal */
268 #define X86_FEATURE_AVX512CD ( 9*32+28) /* "avx512cd" AVX-512 Conflict Detection */
270 #define X86_FEATURE_AVX512BW ( 9*32+30) /* "avx512bw" AVX-512 BW (Byte/Word granular) Instructions…
271 #define X86_FEATURE_AVX512VL ( 9*32+31) /* "avx512vl" AVX-512 VL (128/256 Vector Length) Extension…
277 #define X86_FEATURE_XSAVES (10*32+ 3) /* "xsaves" XSAVES/XRSTORS instructions */
281 * Extended auxiliary flags: Linux defined - for features scattered in various
289 #define X86_FEATURE_CQM_MBM_LOCAL (11*32+ 3) /* "cqm_mbm_local" LLC Local MBM monitoring */
293 #define X86_FEATURE_PER_THREAD_MBA (11*32+ 7) /* Per-thread Memory Bandwidth Allocation */
319 /* Intel-defined CPU features, CPUID level 0x00000007:1 (EAX), word 12 */
327 #define X86_FEATURE_FZRM (12*32+10) /* Fast zero-length REP MOVSB */
332 #define X86_FEATURE_WRMSRNS (12*32+19) /* Non-serializing WRMSR */
337 /* AMD-defined CPU features, CPUID level 0x80000008 (EBX), word 13 */
346 …E_AMD_STIBP_ALWAYS_ON (13*32+17) /* Single Thread Indirect Branch Predictors always-on preferred */
363 #define X86_FEATURE_HWP (14*32+ 7) /* "hwp" Intel Hardware P-states */
375 #define X86_FEATURE_NRIPS (15*32+ 3) /* "nrip_save" SVM next_rip save */
378 #define X86_FEATURE_FLUSHBYASID (15*32+ 6) /* "flushbyasid" Flush-by-ASID support */
390 /* Intel-defined CPU features, CPUID level 0x00000007:0 (ECX), word 16 */
393 #define X86_FEATURE_PKU (16*32+ 3) /* "pku" Protection Keys for Userspace */
400 #define X86_FEATURE_VPCLMULQDQ (16*32+10) /* "vpclmulqdq" Carry-Less Multiplication Double Quadwor…
402 …512_BITALG (16*32+12) /* "avx512_bitalg" Support for VPOPCNT[B,W] and VPSHUF-BITQMB instructions */
405 #define X86_FEATURE_LA57 (16*32+16) /* "la57" 5-level page tables */
414 /* AMD-defined CPU features, CPUID level 0x80000007 (EBX), word 17 */
417 #define X86_FEATURE_SMCA (17*32+ 3) /* "smca" Scalable MCA */
419 /* Intel-defined CPU features, CPUID level 0x00000007:0 (EDX), word 18 */
420 #define X86_FEATURE_AVX512_4VNNIW (18*32+ 2) /* "avx512_4vnniw" AVX-512 Neural Network Instructions…
421 #define X86_FEATURE_AVX512_4FMAPS (18*32+ 3) /* "avx512_4fmaps" AVX-512 Multiply Accumulation Singl…
423 #define X86_FEATURE_AVX512_VP2INTERSECT (18*32+ 8) /* "avx512_vp2intersect" AVX-512 Intersect for D…
445 /* AMD-defined memory encryption features, CPUID level 0x8000001f (EAX), word 19 */
449 #define X86_FEATURE_SEV_ES (19*32+ 3) /* "sev_es" Secure Encrypted Virtualization - Encrypted Stat…
450 #define X86_FEATURE_SEV_SNP (19*32+ 4) /* "sev_snp" Secure Encrypted Virtualization - Secure Neste…
452 #define X86_FEATURE_SME_COHERENT (19*32+10) /* hardware-enforced cache coherency */
453 #define X86_FEATURE_DEBUG_SWAP (19*32+14) /* "debug_swap" SEV-ES full debug state swap support */
457 #define X86_FEATURE_HV_INUSE_WR_ALLOWED (19*32+30) /* Allow Write to in-use hypervisor-owned pages …
459 /* AMD-defined Extended Feature 2 EAX, CPUID level 0x80000021 (EAX), word 20 */
461 #define X86_FEATURE_WRMSR_XX_BASE_NS (20*32+ 1) /* WRMSR to {FS,GS,KERNEL_GS}_BASE is non-serializi…
473 * Extended auxiliary flags: Linux defined - for features scattered in various
481 #define X86_FEATURE_CLEAR_BHB_HW (21*32+ 3) /* BHI_DIS_S HW control enabled */
495 #define X86_BUG_AMD_TLB_MMATCH X86_BUG(3) /* "tlb_mmatch" AMD Erratum 383 */
503 * 64-bit kernels don't use X86_BUG_ESPFIX. Make the define conditional
506 #define X86_BUG_ESPFIX X86_BUG(9) /* IRET to 16-bit SS corrupts ESP/RSP high bits */
508 #define X86_BUG_NULL_SEG X86_BUG(10) /* "null_seg" Nulling a selector preserves the base */
527 #define X86_BUG_SMT_RSB X86_BUG(29) /* "smt_rsb" CPU is vulnerable to Cross-Thread Return Address…
529 #define X86_BUG_TDX_PW_MCE X86_BUG(31) /* "tdx_pw_mce" CPU may incur #MC if non-TD software does p…
535 #define X86_BUG_BHI X86_BUG(1*32 + 3) /* "bhi" CPU is affected by Branch History Injection */