33 	{ 0x00, 0x18, 0x20 },
34 	{ 0xff, 0x00, 0x20 },
35 	{ 0xfe, 0x00, 0x20 },
65 		return 0;  in amd_cache_northbridges()
75 	for (i = 0; i < amd_northbridges.num; i++) {  in amd_cache_northbridges()
84 			amd_northbridges.num = 0;  in amd_cache_northbridges()
98 	if (!cpuid_edx(0x80000006))  in amd_cache_northbridges()
99 		return 0;  in amd_cache_northbridges()
103 	 * limitations because of E382 and E388 on family 0x10.  in amd_cache_northbridges()
105 	if (boot_cpu_data.x86 == 0x10 &&  in amd_cache_northbridges()
106 	    boot_cpu_data.x86_model >= 0x8 &&  in amd_cache_northbridges()
107 	    (boot_cpu_data.x86_model > 0x9 ||  in amd_cache_northbridges()
108 	     boot_cpu_data.x86_stepping >= 0x1))  in amd_cache_northbridges()
111 	if (boot_cpu_data.x86 == 0x15)  in amd_cache_northbridges()
114 	/* L3 cache partitioning is supported on family 0x15 */  in amd_cache_northbridges()
115 	if (boot_cpu_data.x86 == 0x15)  in amd_cache_northbridges()
118 	return 0;  in amd_cache_northbridges()
128 	u32 vendor = device & 0xffff;  in early_is_amd_nb()
154 	if (boot_cpu_data.x86 < 0x10 ||  in amd_get_mmconfig_range()
179 		return 0;  in amd_get_subcaches()
181 	pci_read_config_dword(link, 0x1d4, &mask);  in amd_get_subcaches()
183 	return (mask >> (4 * cpu_data(cpu).topo.core_id)) & 0xf;  in amd_get_subcaches()
193 	if (!amd_nb_has_feature(AMD_NB_L3_PARTITIONING) || mask > 0xf)  in amd_set_subcaches()
197 	if (reset == 0) {  in amd_set_subcaches()
198 		pci_read_config_dword(nb->link, 0x1d4, &reset);  in amd_set_subcaches()
199 		pci_read_config_dword(nb->misc, 0x1b8, &ban);  in amd_set_subcaches()
200 		ban &= 0x180000;  in amd_set_subcaches()
204 	if (mask != 0xf) {  in amd_set_subcaches()
205 		pci_read_config_dword(nb->misc, 0x1b8, &reg);  in amd_set_subcaches()
206 		pci_write_config_dword(nb->misc, 0x1b8, reg & ~0x180000);  in amd_set_subcaches()
211 	mask |= (0xf ^ (1 << cuid)) << 26;  in amd_set_subcaches()
213 	pci_write_config_dword(nb->link, 0x1d4, mask);  in amd_set_subcaches()
216 	pci_read_config_dword(nb->link, 0x1d4, &reg);  in amd_set_subcaches()
218 		pci_read_config_dword(nb->misc, 0x1b8, &reg);  in amd_set_subcaches()
219 		reg &= ~0x180000;  in amd_set_subcaches()
220 		pci_write_config_dword(nb->misc, 0x1b8, reg | ban);  in amd_set_subcaches()
223 	return 0;  in amd_set_subcaches()
240 	for (i = 0; i != amd_northbridges.num; i++)  in amd_cache_gart()
241 		pci_read_config_dword(node_to_amd_nb(i)->misc, 0x9c, &flush_words[i]);  in amd_cache_gart()
260 	flushed = 0;  in amd_flush_garts()
261 	for (i = 0; i < amd_northbridges.num; i++) {  in amd_flush_garts()
262 		pci_write_config_dword(node_to_amd_nb(i)->misc, 0x9c,  in amd_flush_garts()
266 	for (i = 0; i < amd_northbridges.num; i++) {  in amd_flush_garts()
271 					      0x9c, &w);  in amd_flush_garts()
285 #define MSR_AMD64_IC_CFG 0xC0011021  in __fix_erratum_688()
297 	if (boot_cpu_data.x86 != 0x14)  in fix_erratum_688()
303 	F4 = node_to_amd_nb(0)->link;  in fix_erratum_688()
307 	if (pci_read_config_dword(F4, 0x164, &val))  in fix_erratum_688()
313 	on_each_cpu(__fix_erratum_688, NULL, 0);  in fix_erratum_688()
322 		return 0;  in init_amd_nbs()
329 	return 0;  in init_amd_nbs()