Lines Matching full:apic
3 * Intel IO-APIC support for multi-Pentium hosts.
10 * (c) 1999, Multiple IO-APIC support, developed by
25 * - SiS APIC rmw bug:
67 #include <asm/apic.h>
90 int apic, pin; member
112 /* I/O APIC config */
114 /* IO APIC gsi routing info */
193 /* disable IO-APIC */ in parse_noapic()
204 apic_pr_verbose("Int: type %d, pol %d, trig %d, bus %02x, IRQ %02x, APIC ID %x, APIC INT %02x\n", in mp_save_irq()
264 static inline void io_apic_eoi(unsigned int apic, unsigned int vector) in io_apic_eoi() argument
266 struct io_apic __iomem *io_apic = io_apic_base(apic); in io_apic_eoi()
271 unsigned int native_io_apic_read(unsigned int apic, unsigned int reg) in native_io_apic_read() argument
273 struct io_apic __iomem *io_apic = io_apic_base(apic); in native_io_apic_read()
279 static void io_apic_write(unsigned int apic, unsigned int reg, in io_apic_write() argument
282 struct io_apic __iomem *io_apic = io_apic_base(apic); in io_apic_write()
288 static struct IO_APIC_route_entry __ioapic_read_entry(int apic, int pin) in __ioapic_read_entry() argument
292 entry.w1 = io_apic_read(apic, 0x10 + 2 * pin); in __ioapic_read_entry()
293 entry.w2 = io_apic_read(apic, 0x11 + 2 * pin); in __ioapic_read_entry()
298 static struct IO_APIC_route_entry ioapic_read_entry(int apic, int pin) in ioapic_read_entry() argument
301 return __ioapic_read_entry(apic, pin); in ioapic_read_entry()
305 * When we write a new IO APIC routing entry, we need to write the high
310 static void __ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e) in __ioapic_write_entry() argument
312 io_apic_write(apic, 0x11 + 2*pin, e.w2); in __ioapic_write_entry()
313 io_apic_write(apic, 0x10 + 2*pin, e.w1); in __ioapic_write_entry()
316 static void ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e) in ioapic_write_entry() argument
319 __ioapic_write_entry(apic, pin, e); in ioapic_write_entry()
323 * When we mask an IO APIC routing entry, we need to write the low
327 static void ioapic_mask_entry(int apic, int pin) in ioapic_mask_entry() argument
332 io_apic_write(apic, 0x10 + 2*pin, e.w1); in ioapic_mask_entry()
333 io_apic_write(apic, 0x11 + 2*pin, e.w2); in ioapic_mask_entry()
341 static bool add_pin_to_irq_node(struct mp_chip_data *data, int node, int apic, int pin) in add_pin_to_irq_node() argument
347 if (entry->apic == apic && entry->pin == pin) in add_pin_to_irq_node()
353 pr_err("Cannot allocate irq_pin_list (%d,%d,%d)\n", node, apic, pin); in add_pin_to_irq_node()
357 entry->apic = apic; in add_pin_to_irq_node()
363 static void __remove_pin_from_irq(struct mp_chip_data *data, int apic, int pin) in __remove_pin_from_irq() argument
368 if (entry->apic == apic && entry->pin == pin) { in __remove_pin_from_irq()
384 io_apic_write(entry->apic, 0x10 + 2 * entry->pin, data->entry.w1); in io_apic_modify_irq()
391 * Synchronize the IO-APIC and the CPU by doing a dummy read from the
392 * IO-APIC
398 io_apic = io_apic_base(entry->apic); in io_apic_sync()
424 * IO-APIC versions below 0x20 don't support EOI register.
427 * 1Xh I/OAPIC or I/O(x)APIC which are not PCI 2.2 Compliant
428 * 2Xh I/O(x)APIC which is PCI 2.2 Compliant
431 * Some of the Intel ICH Specs (ICH2 to ICH5) documents the io-apic
433 * use io-apic's of version 0x20.
435 * For IO-APIC's with EOI register, we use that to do an explicit EOI.
439 static void __eoi_ioapic_pin(int apic, int pin, int vector) in __eoi_ioapic_pin() argument
441 if (mpc_ioapic_ver(apic) >= 0x20) { in __eoi_ioapic_pin()
442 io_apic_eoi(apic, vector); in __eoi_ioapic_pin()
446 entry = entry1 = __ioapic_read_entry(apic, pin); in __eoi_ioapic_pin()
452 __ioapic_write_entry(apic, pin, entry1); in __eoi_ioapic_pin()
455 __ioapic_write_entry(apic, pin, entry); in __eoi_ioapic_pin()
465 __eoi_ioapic_pin(entry->apic, entry->pin, vector); in eoi_ioapic_pin()
468 static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin) in clear_IO_APIC_pin() argument
473 entry = ioapic_read_entry(apic, pin); in clear_IO_APIC_pin()
483 ioapic_write_entry(apic, pin, entry); in clear_IO_APIC_pin()
484 entry = ioapic_read_entry(apic, pin); in clear_IO_APIC_pin()
495 ioapic_write_entry(apic, pin, entry); in clear_IO_APIC_pin()
498 __eoi_ioapic_pin(apic, pin, entry.vector); in clear_IO_APIC_pin()
502 * Clear the rest of the bits in the IO-APIC RTE except for the mask in clear_IO_APIC_pin()
505 ioapic_mask_entry(apic, pin); in clear_IO_APIC_pin()
506 entry = ioapic_read_entry(apic, pin); in clear_IO_APIC_pin()
508 pr_err("Unable to reset IRR for apic: %d, pin :%d\n", in clear_IO_APIC_pin()
509 mpc_ioapic_id(apic), pin); in clear_IO_APIC_pin()
514 int apic, pin; in clear_IO_APIC() local
516 for_each_ioapic_pin(apic, pin) in clear_IO_APIC()
517 clear_IO_APIC_pin(apic, pin); in clear_IO_APIC()
554 * Saves all the IO-APIC RTE's
558 int apic, pin; in save_ioapic_entries() local
561 for_each_ioapic(apic) { in save_ioapic_entries()
562 if (!ioapics[apic].saved_registers) { in save_ioapic_entries()
567 for_each_pin(apic, pin) in save_ioapic_entries()
568 ioapics[apic].saved_registers[pin] = ioapic_read_entry(apic, pin); in save_ioapic_entries()
575 * Mask all IO APIC entries.
579 int apic, pin; in mask_ioapic_entries() local
581 for_each_ioapic(apic) { in mask_ioapic_entries()
582 if (!ioapics[apic].saved_registers) in mask_ioapic_entries()
585 for_each_pin(apic, pin) { in mask_ioapic_entries()
588 entry = ioapics[apic].saved_registers[pin]; in mask_ioapic_entries()
591 ioapic_write_entry(apic, pin, entry); in mask_ioapic_entries()
598 * Restore IO APIC entries which was saved in the ioapic structure.
602 int apic, pin; in restore_ioapic_entries() local
604 for_each_ioapic(apic) { in restore_ioapic_entries()
605 if (!ioapics[apic].saved_registers) in restore_ioapic_entries()
608 for_each_pin(apic, pin) in restore_ioapic_entries()
609 ioapic_write_entry(apic, pin, ioapics[apic].saved_registers[pin]); in restore_ioapic_entries()
1136 apic_pr_verbose("apic %d pin %d not connected\n", in setup_IO_APIC_irqs()
1149 static void io_apic_print_entries(unsigned int apic, unsigned int nr_entries) in io_apic_print_entries() argument
1155 apic_dbg("IOAPIC %d:\n", apic); in io_apic_print_entries()
1157 entry = ioapic_read_entry(apic, i); in io_apic_print_entries()
1190 apic_dbg("IO APIC #%d......\n", mpc_ioapic_id(ioapic_idx)); in print_IO_APIC()
1192 apic_dbg("....... : physical APIC id: %02X\n", reg_00.bits.ID); in print_IO_APIC()
1198 apic_dbg("....... : IO APIC version: %02X\n", reg_01.bits.version); in print_IO_APIC()
1201 * Some Intel chipsets with IO APIC VERSION of 0x1? don't have reg_02, in print_IO_APIC()
1211 * Some Intel chipsets with IO APIC VERSION of 0x2? don't have reg_02 in print_IO_APIC()
1232 apic_dbg("number of IO-APIC #%d registers: %d.\n", in print_IO_APICs()
1240 printk(KERN_INFO "testing the IO APIC.......................\n"); in print_IO_APICs()
1262 pr_cont("-> %d:%d", entry->apic, entry->pin); in print_IO_APICs()
1270 static struct { int pin, apic; } ioapic_i8259 = { -1, -1 }; member
1274 int i8259_apic, i8259_pin, apic, pin; in enable_IO_APIC() local
1282 for_each_ioapic_pin(apic, pin) { in enable_IO_APIC()
1284 struct IO_APIC_route_entry entry = ioapic_read_entry(apic, pin); in enable_IO_APIC()
1291 ioapic_i8259.apic = apic; in enable_IO_APIC()
1310 ioapic_i8259.apic = i8259_apic; in enable_IO_APIC()
1313 if (((ioapic_i8259.apic != i8259_apic) || (ioapic_i8259.pin != i8259_pin)) && in enable_IO_APIC()
1317 /* Do not trust the IO-APIC being empty at bootup */ in enable_IO_APIC()
1340 /* Add it to the IO-APIC irq-routing table */ in native_restore_boot_irq_mode()
1341 ioapic_write_entry(ioapic_i8259.apic, ioapic_i8259.pin, entry); in native_restore_boot_irq_mode()
1358 * function to set the IO-APIC physical IDs based on the
1388 pr_err(FW_BUG "IO-APIC#%d ID is %d in the MPC table!...\n", in setup_ioapic_ids_from_mpc_nocheck()
1395 * Sanity check, is the ID really free? Every APIC in a in setup_ioapic_ids_from_mpc_nocheck()
1400 pr_err(FW_BUG "IO-APIC#%d ID %d is already used!...\n", in setup_ioapic_ids_from_mpc_nocheck()
1406 panic("Max APIC ID exceeded!\n"); in setup_ioapic_ids_from_mpc_nocheck()
1434 apic_pr_verbose("...changing IO-APIC physical APIC ID to %d ...", in setup_ioapic_ids_from_mpc_nocheck()
1456 * Don't check I/O APIC IDs for xAPIC systems. They have in setup_ioapic_ids_from_mpc()
1457 * no meaning without the serial APIC bus. in setup_ioapic_ids_from_mpc()
1515 * - timer IRQ defaults to IO-APIC IRQ
1535 * ticks in a non-ExtINT mode. Also the local APIC in timer_irq_works()
1557 * Starting up a edge-triggered IO-APIC interrupt is nasty - we need to
1591 e.w1 = io_apic_read(entry->apic, 0x10 + pin*2); in io_apic_level_ack_pending()
1669 * of I/O APIC (that's the 82093AA and cores integrated into various in ioapic_ack_level()
1681 * trigger mode gets detected in the TMR of a local APIC for a in ioapic_ack_level()
1690 * level-triggered io-apic interrupt will be seen as an edge in ioapic_ack_level()
1692 * to be broadcasted to the IO-APIC's which will clear the remoteIRR in ioapic_ack_level()
1693 * corresponding to the level-triggered interrupt. Hence on IO-APIC's in ioapic_ack_level()
1695 * remote IRR and on IO-APIC's which don't have an EOI register, in ioapic_ack_level()
1710 * message via io-apic EOI register write or simulating it using in ioapic_ack_level()
1730 * intr-remapping table entry. Hence for the io-apic in ioapic_ir_ack_level()
1794 __ioapic_write_entry(entry->apic, entry->pin, mpd->entry); in ioapic_configure_entry()
1839 rentry = __ioapic_read_entry(p->apic, p->pin); in ioapic_irq_get_chip_state()
1843 * irrelevant because the IO-APIC treats them as fire and in ioapic_irq_get_chip_state()
1855 .name = "IO-APIC",
1869 .name = "IR-IO-APIC",
1904 * The local APIC irq-chip implementation:
1926 .name = "local-APIC",
1949 int apic, pin, i; in unlock_ExtINT_logic() local
1957 apic = find_isa_irq_apic(8, mp_INT); in unlock_ExtINT_logic()
1958 if (apic == -1) { in unlock_ExtINT_logic()
1963 entry0 = ioapic_read_entry(apic, pin); in unlock_ExtINT_logic()
1964 clear_IO_APIC_pin(apic, pin); in unlock_ExtINT_logic()
1978 ioapic_write_entry(apic, pin, entry1); in unlock_ExtINT_logic()
1995 clear_IO_APIC_pin(apic, pin); in unlock_ExtINT_logic()
1997 ioapic_write_entry(apic, pin, entry0); in unlock_ExtINT_logic()
2034 if (entry->apic == oldapic && entry->pin == oldpin) { in replace_pin_at_irq_node()
2035 entry->apic = newapic; in replace_pin_at_irq_node()
2041 /* Old apic/pin didn't exist, so just add a new one */ in replace_pin_at_irq_node()
2072 * wire has to be disabled in the local APIC. Also in check_timer()
2075 * watchdog as that APIC treats NMIs as level-triggered. in check_timer()
2085 apic2 = ioapic_i8259.apic; in check_timer()
2092 * I/O APIC input from the cascaded 8259A as the timer in check_timer()
2098 panic_if_irq_remap(FW_BUG "Timer not connected to IO-APIC"); in check_timer()
2129 panic_if_irq_remap("timer doesn't work through Interrupt-remapped IO-APIC"); in check_timer()
2132 pr_err("..MP-BIOS bug: 8254 timer not connected to IO-APIC\n"); in check_timer()
2135 pr_info("..... (found apic %d pin %d) ...\n", apic2, pin2); in check_timer()
2137 * legacy devices should be connected to IO APIC #0 in check_timer()
2188 panic("IO-APIC + timer doesn't work! Boot with apic=debug and send a " in check_timer()
2196 * to devices. However there may be an I/O APIC pin available for
2202 * of an override it would be treated as an ordinary ISA I/O APIC
2206 * the same ExtINT cascade interrupt to drive the local APIC of the
2208 * the I/O APIC in all cases now. No actual device should request
2230 fn = irq_domain_alloc_named_id_fwnode("IO-APIC", mpc_ioapic_id(ioapic)); in mp_irqdomain_create()
2283 apic_pr_verbose("ENABLING IO-APIC IRQs\n"); in setup_IO_APIC()
2287 /* Set up IO-APIC IRQ routing. */ in setup_IO_APIC()
2361 * always 0. gsi_top can be 0 if there is no IO/APIC registered. in arch_dynirq_lower_bound()
2389 /* Every APIC in a system must have a unique ID */ in io_apic_get_unique_id()
2529 * Ensure fixmaps for IO-APIC MMIO respect memory encryption pgprot in io_apic_set_fixmap()
2554 pr_err("WARNING: bogus zero IO-APIC address found in MPTABLE, " in io_apic_init_mappings()
2555 "disabling IO/APIC support!\n"); in io_apic_init_mappings()
2587 pr_err("IO APIC resources couldn't be allocated.\n"); in ioapic_insert_resources()
2641 pr_warn("I/O APIC 0x%x registers return all ones, skipping!\n", in bad_ioapic_register()
2673 pr_warn("Bogus (zero) I/O APIC address found, skipping!\n"); in mp_register_ioapic()
2825 * Configure the I/O-APIC specific fields in the routing entry.
2827 * This is important to setup the I/O-APIC specific bits (is_level,
2829 * provide the routing information and is oblivious of the I/O-APIC