Lines Matching +full:4 +full:k
373 c->x86_stepping >= 1 && c->x86_stepping <= 4 && in intel_smp_check()
416 if ((c->x86<<8 | c->x86_model<<4 | c->x86_stepping) < 0x633) in intel_workarounds()
448 if (boot_cpu_has(X86_FEATURE_APIC) && (c->x86<<8 | c->x86_model<<4) == 0x520 && in intel_workarounds()
458 case 4: /* 486: untested */ in intel_workarounds()
629 * Intel Quark SoC X1000 contains a 4-way set associative in intel_size_cache()
630 * 16K cache with a 16 byte cache line and 256 lines per tag in intel_size_cache()
663 * exception: it implies 4 dTLB entries for 1GB pages 32 dTLB entries
664 * for 2MB or 4MB pages. Encode descriptor 0x63 dTLB entry count for
665 * 2MB/4MB pages here, as its count for dTLB 1GB pages is already at the
671 { 0x01, TLB_INST_4K, 32, " TLB_INST 4 KByte pages, 4-way set associative" },
672 { 0x02, TLB_INST_4M, 2, " TLB_INST 4 MByte pages, full associative" },
673 { 0x03, TLB_DATA_4K, 64, " TLB_DATA 4 KByte pages, 4-way set associative" },
674 { 0x04, TLB_DATA_4M, 8, " TLB_DATA 4 MByte pages, 4-way set associative" },
675 { 0x05, TLB_DATA_4M, 32, " TLB_DATA 4 MByte pages, 4-way set associative" },
676 { 0x0b, TLB_INST_4M, 4, " TLB_INST 4 MByte pages, 4-way set associative" },
677 { 0x4f, TLB_INST_4K, 32, " TLB_INST 4 KByte pages" },
678 { 0x50, TLB_INST_ALL, 64, " TLB_INST 4 KByte and 2-MByte or 4-MByte pages" },
679 { 0x51, TLB_INST_ALL, 128, " TLB_INST 4 KByte and 2-MByte or 4-MByte pages" },
680 { 0x52, TLB_INST_ALL, 256, " TLB_INST 4 KByte and 2-MByte or 4-MByte pages" },
681 { 0x55, TLB_INST_2M_4M, 7, " TLB_INST 2-MByte or 4-MByte pages, fully associative" },
682 { 0x56, TLB_DATA0_4M, 16, " TLB_DATA0 4 MByte pages, 4-way set associative" },
683 { 0x57, TLB_DATA0_4K, 16, " TLB_DATA0 4 KByte pages, 4-way associative" },
684 { 0x59, TLB_DATA0_4K, 16, " TLB_DATA0 4 KByte pages, fully associative" },
685 { 0x5a, TLB_DATA0_2M_4M, 32, " TLB_DATA0 2-MByte or 4 MByte pages, 4-way set associative" },
686 { 0x5b, TLB_DATA_4K_4M, 64, " TLB_DATA 4 KByte and 4 MByte pages" },
687 { 0x5c, TLB_DATA_4K_4M, 128, " TLB_DATA 4 KByte and 4 MByte pages" },
688 { 0x5d, TLB_DATA_4K_4M, 256, " TLB_DATA 4 KByte and 4 MByte pages" },
689 { 0x61, TLB_INST_4K, 48, " TLB_INST 4 KByte pages, full associative" },
690 { 0x63, TLB_DATA_1G_2M_4M, 4, " TLB_DATA 1 GByte pages, 4-way set associative"
691 " (plus 32 entries TLB_DATA 2 MByte or 4 MByte pages, not encoded here)" },
692 { 0x6b, TLB_DATA_4K, 256, " TLB_DATA 4 KByte pages, 8-way associative" },
693 { 0x6c, TLB_DATA_2M_4M, 128, " TLB_DATA 2 MByte or 4 MByte pages, 8-way associative" },
695 { 0x76, TLB_INST_2M_4M, 8, " TLB_INST 2-MByte or 4-MByte pages, fully associative" },
696 { 0xb0, TLB_INST_4K, 128, " TLB_INST 4 KByte pages, 4-way set associative" },
697 { 0xb1, TLB_INST_2M_4M, 4, " TLB_INST 2M pages, 4-way, 8 entries or 4M pages, 4-way entries" },
698 { 0xb2, TLB_INST_4K, 64, " TLB_INST 4KByte pages, 4-way set associative" },
699 { 0xb3, TLB_DATA_4K, 128, " TLB_DATA 4 KByte pages, 4-way set associative" },
700 { 0xb4, TLB_DATA_4K, 256, " TLB_DATA 4 KByte pages, 4-way associative" },
701 { 0xb5, TLB_INST_4K, 64, " TLB_INST 4 KByte pages, 8-way set associative" },
702 { 0xb6, TLB_INST_4K, 128, " TLB_INST 4 KByte pages, 8-way set associative" },
703 { 0xba, TLB_DATA_4K, 64, " TLB_DATA 4 KByte pages, 4-way associative" },
704 { 0xc0, TLB_DATA_4K_4M, 8, " TLB_DATA 4 KByte and 4 MByte pages, 4-way associative" },
705 { 0xc1, STLB_4K_2M, 1024, " STLB 4 KByte and 2 MByte pages, 8-way associative" },
706 { 0xc2, TLB_DATA_2M_4M, 16, " TLB_DATA 2 MByte/4MByte pages, 4-way associative" },
707 { 0xca, STLB_4K, 512, " STLB 4 KByte pages, 4-way associative" },
713 unsigned char k; in intel_tlb_lookup() local
718 for (k = 0; intel_tlb_table[k].descriptor != desc && in intel_tlb_lookup()
719 intel_tlb_table[k].descriptor != 0; k++) in intel_tlb_lookup()
722 if (intel_tlb_table[k].tlb_type == 0) in intel_tlb_lookup()
725 switch (intel_tlb_table[k].tlb_type) { in intel_tlb_lookup()
727 if (tlb_lli_4k[ENTRIES] < intel_tlb_table[k].entries) in intel_tlb_lookup()
728 tlb_lli_4k[ENTRIES] = intel_tlb_table[k].entries; in intel_tlb_lookup()
729 if (tlb_lld_4k[ENTRIES] < intel_tlb_table[k].entries) in intel_tlb_lookup()
730 tlb_lld_4k[ENTRIES] = intel_tlb_table[k].entries; in intel_tlb_lookup()
733 if (tlb_lli_4k[ENTRIES] < intel_tlb_table[k].entries) in intel_tlb_lookup()
734 tlb_lli_4k[ENTRIES] = intel_tlb_table[k].entries; in intel_tlb_lookup()
735 if (tlb_lld_4k[ENTRIES] < intel_tlb_table[k].entries) in intel_tlb_lookup()
736 tlb_lld_4k[ENTRIES] = intel_tlb_table[k].entries; in intel_tlb_lookup()
737 if (tlb_lli_2m[ENTRIES] < intel_tlb_table[k].entries) in intel_tlb_lookup()
738 tlb_lli_2m[ENTRIES] = intel_tlb_table[k].entries; in intel_tlb_lookup()
739 if (tlb_lld_2m[ENTRIES] < intel_tlb_table[k].entries) in intel_tlb_lookup()
740 tlb_lld_2m[ENTRIES] = intel_tlb_table[k].entries; in intel_tlb_lookup()
741 if (tlb_lli_4m[ENTRIES] < intel_tlb_table[k].entries) in intel_tlb_lookup()
742 tlb_lli_4m[ENTRIES] = intel_tlb_table[k].entries; in intel_tlb_lookup()
743 if (tlb_lld_4m[ENTRIES] < intel_tlb_table[k].entries) in intel_tlb_lookup()
744 tlb_lld_4m[ENTRIES] = intel_tlb_table[k].entries; in intel_tlb_lookup()
747 if (tlb_lli_4k[ENTRIES] < intel_tlb_table[k].entries) in intel_tlb_lookup()
748 tlb_lli_4k[ENTRIES] = intel_tlb_table[k].entries; in intel_tlb_lookup()
749 if (tlb_lli_2m[ENTRIES] < intel_tlb_table[k].entries) in intel_tlb_lookup()
750 tlb_lli_2m[ENTRIES] = intel_tlb_table[k].entries; in intel_tlb_lookup()
751 if (tlb_lli_4m[ENTRIES] < intel_tlb_table[k].entries) in intel_tlb_lookup()
752 tlb_lli_4m[ENTRIES] = intel_tlb_table[k].entries; in intel_tlb_lookup()
755 if (tlb_lli_4k[ENTRIES] < intel_tlb_table[k].entries) in intel_tlb_lookup()
756 tlb_lli_4k[ENTRIES] = intel_tlb_table[k].entries; in intel_tlb_lookup()
759 if (tlb_lli_4m[ENTRIES] < intel_tlb_table[k].entries) in intel_tlb_lookup()
760 tlb_lli_4m[ENTRIES] = intel_tlb_table[k].entries; in intel_tlb_lookup()
763 if (tlb_lli_2m[ENTRIES] < intel_tlb_table[k].entries) in intel_tlb_lookup()
764 tlb_lli_2m[ENTRIES] = intel_tlb_table[k].entries; in intel_tlb_lookup()
765 if (tlb_lli_4m[ENTRIES] < intel_tlb_table[k].entries) in intel_tlb_lookup()
766 tlb_lli_4m[ENTRIES] = intel_tlb_table[k].entries; in intel_tlb_lookup()
770 if (tlb_lld_4k[ENTRIES] < intel_tlb_table[k].entries) in intel_tlb_lookup()
771 tlb_lld_4k[ENTRIES] = intel_tlb_table[k].entries; in intel_tlb_lookup()
775 if (tlb_lld_4m[ENTRIES] < intel_tlb_table[k].entries) in intel_tlb_lookup()
776 tlb_lld_4m[ENTRIES] = intel_tlb_table[k].entries; in intel_tlb_lookup()
780 if (tlb_lld_2m[ENTRIES] < intel_tlb_table[k].entries) in intel_tlb_lookup()
781 tlb_lld_2m[ENTRIES] = intel_tlb_table[k].entries; in intel_tlb_lookup()
782 if (tlb_lld_4m[ENTRIES] < intel_tlb_table[k].entries) in intel_tlb_lookup()
783 tlb_lld_4m[ENTRIES] = intel_tlb_table[k].entries; in intel_tlb_lookup()
786 if (tlb_lld_4k[ENTRIES] < intel_tlb_table[k].entries) in intel_tlb_lookup()
787 tlb_lld_4k[ENTRIES] = intel_tlb_table[k].entries; in intel_tlb_lookup()
788 if (tlb_lld_4m[ENTRIES] < intel_tlb_table[k].entries) in intel_tlb_lookup()
789 tlb_lld_4m[ENTRIES] = intel_tlb_table[k].entries; in intel_tlb_lookup()
798 if (tlb_lld_1g[ENTRIES] < intel_tlb_table[k].entries) in intel_tlb_lookup()
799 tlb_lld_1g[ENTRIES] = intel_tlb_table[k].entries; in intel_tlb_lookup()
807 unsigned int regs[4]; in intel_detect_tlb()
820 for (j = 0 ; j < 4 ; j++) in intel_detect_tlb()
835 { .family = 4, .model_names =
841 [4] = "486 SL",
844 [8] = "486 DX/4",
845 [9] = "486 DX/4-WB"
854 [4] = "Pentium MMX",
865 [4] = "Pentium II (Deschutes)",
876 [0] = "Pentium 4 (Unknown)",
877 [1] = "Pentium 4 (Willamette)",
878 [2] = "Pentium 4 (Northwood)",
879 [4] = "Pentium 4 (Foster)",
880 [5] = "Pentium 4 (Foster)",