48 	if (boot_cpu_data.cpuid_level < 0 ||  in jailhouse_cpuid_base()
50 		return 0;  in jailhouse_cpuid_base()
52 	return hypervisor_cpuid_base("Jailhouse\0\0\0", 0);  in jailhouse_cpuid_base()
62 	memset(now, 0, sizeof(*now));  in jailhouse_get_wallclock()
103 	register_lapic_address(0xfee00000);  in jailhouse_parse_smp_config()
105 	for (cpu = 0; cpu < setup_data.v1.num_cpus; cpu++)  in jailhouse_parse_smp_config()
111 		mp_register_ioapic(0, 0xfec00000, gsi_top, &ioapic_cfg);  in jailhouse_parse_smp_config()
137 	if (pcibios_last_bus < 0)  in jailhouse_pci_arch_init()
138 		pcibios_last_bus = 0xff;  in jailhouse_pci_arch_init()
142 		pci_mmconfig_add(0, 0, pcibios_last_bus,  in jailhouse_pci_arch_init()
148 	return 0;  in jailhouse_pci_arch_init()
160 	static const u16 pcuart_base[] = {0x3f8, 0x2f8, 0x3e8, 0x2e8};  in jailhouse_serial_fixup()
163 	for (n = 0; n < ARRAY_SIZE(pcuart_base); n++) {  in jailhouse_serial_fixup()
168 			pr_info("Enabling UART%u (port 0x%lx)\n", n,  in jailhouse_serial_fixup()
173 			up->iobase = 0;  in jailhouse_serial_fixup()
215 	x86_platform.legacy.rtc			= 0;  in jailhouse_init_platform()
216 	x86_platform.legacy.warm_reset		= 0;  in jailhouse_init_platform()
248 	if (setup_data.hdr.version == 0 ||  in jailhouse_init_platform()
261 	pci_probe = 0;  in jailhouse_init_platform()
278 	return jailhouse_cpuid_base() != 0;  in jailhouse_paravirt()