36 unsigned int __read_mostly cpu_khz;	/* TSC clocks / usec, not used here */
45  * TSC can be unstable due to cpufreq or due to unsynced TSCs
245 	 * Fall back to jiffies if there's no TSC available:  in native_sched_clock()
246 	 * ( But note that we still use it if the TSC is marked  in native_sched_clock()
258  * Generate a sched_clock if you already have a TSC value.
260 u64 native_sched_clock_from_tsc(u64 tsc)  in native_sched_clock_from_tsc()  argument
262 	return cycles_2_ns(tsc);  in native_sched_clock_from_tsc()
306  * disable flag for tsc. Takes effect by clearing the TSC cpu flag
333 			pr_alert("%s: Overriding earlier tsc=watchdog with tsc=nowatchdog\n",  in tsc_setup()
341 			pr_alert("%s: tsc=watchdog overridden by earlier tsc=nowatchdog\n",  in tsc_setup()
349 __setup("tsc=", tsc_setup);
355  * Read TSC and the reference counters. Take care of any disturbances
377  * Calculate the TSC frequency from HPET reference
394  * Calculate the TSC frequency from PMTimer reference
423  * Try to calibrate the TSC against the Programmable
424  * Interrupt Timer and return the frequency of the TSC
431 	u64 tsc, t1, t2, delta;  in pit_calibrate_tsc()  local
461 	tsc = t1 = t2 = get_cycles();  in pit_calibrate_tsc()
468 		delta = t2 - tsc;  in pit_calibrate_tsc()
469 		tsc = t2;  in pit_calibrate_tsc()
511  *    see the same MSB (and overhead like doing a single TSC
527  * use the TSC value at the transitions to calculate a pretty
528  * good value for the TSC frequency.
540 	u64 tsc = 0, prev_tsc = 0;  in pit_expect_msb()  local
545 		prev_tsc = tsc;  in pit_expect_msb()
546 		tsc = get_cycles();  in pit_expect_msb()
549 	*tscp = tsc;  in pit_expect_msb()
553 	 * will be based on the error terms on the TSC values.  in pit_expect_msb()
570 	u64 tsc, delta;  in quick_pit_calibrate()  local
602 	if (pit_expect_msb(0xff, &tsc, &d1)) {  in quick_pit_calibrate()
607 			delta -= tsc;  in quick_pit_calibrate()
625 			 * all TSC reads were stable wrt the PIT.  in quick_pit_calibrate()
635 	pr_info("Fast TSC calibration failed\n");  in quick_pit_calibrate()
645 	 * any odd delays anywhere, and the TSC reads are  in quick_pit_calibrate()
654 	pr_info("Fast TSC calibration using PIT\n");  in quick_pit_calibrate()
659  * native_calibrate_tsc - determine TSC frequency
660  * Determine TSC frequency via CPUID, else return 0.
675 	/* CPUID 15H TSC/Crystal ratio, plus optionally Crystal Hz */  in native_calibrate_tsc()
693 	 * TSC frequency reported directly by CPUID is a "hardware reported"  in native_calibrate_tsc()
717 	 * For Atom SoCs TSC is the only reliable clocksource.  in native_calibrate_tsc()
718 	 * Mark TSC reliable so no watchdog on it.  in native_calibrate_tsc()
772 	 * zero. In each wait loop iteration we read the TSC and check  in pit_hpet_ptimer_calibrate_cpu()
782 	 * We use separate TSC readouts and check inside of the  in pit_hpet_ptimer_calibrate_cpu()
809 		/* Pick the lowest PIT TSC calibration so far */  in pit_hpet_ptimer_calibrate_cpu()
864 		/* We don't have an alternative source, disable TSC */  in pit_hpet_ptimer_calibrate_cpu()
870 		/* The alternative source failed as well, disable TSC */  in pit_hpet_ptimer_calibrate_cpu()
969  * Even on processors with invariant TSC, TSC gets reset in some the
970  * ACPI system sleep states. And in some systems BIOS seem to reinit TSC to
1008  * Frequency scaling support. Adjust the TSC based timer when the CPU frequency
1011  * NOTE: On SMP the situation is not fixable in general, so simply mark the TSC
1075  * If ART is present detect the numerator:denominator to convert to TSC
1085 	 * Don't enable ART in a VM, non-stop TSC and TSC_ADJUST required,  in detect_art()
1086 	 * and the TSC counter resets must not occur asynchronously.  in detect_art()
1116  * We used to compare the TSC to the cycle_last value in the clocksource
1119  * xtime/vsyscall_gtod lock and the other CPU reads a TSC value which
1120  * is smaller than the cycle_last reference value due to a TSC which
1145 	pr_info("Marking TSC unstable due to clocksource watchdog\n");  in tsc_cs_mark_unstable()
1167 	.name			= "tsc-early",
1185  * this one will immediately take over. We will only register if TSC has
1189 	.name			= "tsc",
1215 	pr_info("Marking TSC unstable due to %s\n", reason);  in mark_tsc_unstable()
1244 		/* Geode_LX - the OLPC CPU has a very reliable TSC */  in check_system_tsc_reliable()
1254 	 *  - TSC running at constant frequency  in check_system_tsc_reliable()
1255 	 *  - TSC which does not stop in C-States  in check_system_tsc_reliable()
1268  * Make an educated guess if the TSC is trustworthy and synchronized
1288 	 * Exceptions must mark TSC as unstable:  in unsynchronized_tsc()
1302  * tsc_refine_calibration_work - Further refine tsc freq calibration
1306  * second to further refine the TSC freq value. Since this is
1323 	/* Don't bother refining TSC on unstable systems */  in tsc_refine_calibration_work()
1366 …pr_warn("Warning: TSC freq calibrated by CPUID/MSR differs from what is calibrated by HW timer, pl…  in tsc_refine_calibration_work()
1367 			pr_info("Previous calibrated TSC freq:\t %lu.%03lu MHz\n",  in tsc_refine_calibration_work()
1372 		pr_info("TSC freq recalibrated by [%s]:\t %lu.%03lu MHz\n",  in tsc_refine_calibration_work()
1385 	pr_info("Refined TSC clocksource calibration: %lu.%03lu MHz\n",  in tsc_refine_calibration_work()
1389 	/* Inform the TSC deadline clockevent devices about the recalibration */  in tsc_refine_calibration_work()
1424 	 * When TSC frequency is known (retrieved via MSR or CPUID), we skip  in init_tsc_clocksource()
1450 	/* Make sure that cpu and tsc are not already calibrated */  in determine_cpu_tsc_frequencies()
1485 		pr_info("Detected %lu.%03lu MHz TSC",  in determine_cpu_tsc_frequencies()
1505 	/* Sanitize TSC ADJUST before cyc2ns gets initialized */  in tsc_enable_sched_clock()
1515 	/* Don't change UV TSC multi-chassis synchronization */  in tsc_early_init()
1543 			mark_tsc_unstable("could not calculate TSC khz");  in tsc_init()
1582 	 * If TSC has constant frequency and TSC is synchronized across  in calibrate_delay_is_known()
1589 	 * If TSC has constant frequency and TSC is not synchronized across  in calibrate_delay_is_known()